Integrated circuit margin measurement for structural testing

A method for testing a semiconductor integrated circuit (IC), the method comprising:

• providing a semiconductor IC that comprises a timing margin measurement sensor, wherein the timing margin measurement sensor comprises:
• (i) a signal path combiner comprising:
• (a) a plurality of input paths, each connected to an input of a flip-flop of multiple flip-flops that are comprised in parallel bit paths of a data source in the IC, wherein each of the parallel bit paths terminates with a different one of the multiple flip-flops, and (b) an output,
• wherein the signal path combiner is configured such that each signal received on a different one of the flip-flops of the data source is also received by a respective one of the plurality of input paths of the signal path combiner;
• (ii) a delay circuit comprising:
• (a) an output, and (b) an input connected to the signal path combiner output,
• wherein the delay circuit is configured to apply, at different times, different respective delays to a signal received at the input of the delay circuit, to provide, at the output of the delay circuit, different delayed signals respective of the different delays;
• and
• (iii) a comparison circuit connected to:
• (a) the output of the delay circuit, and (b) the output of the signal path combiner,
• wherein the comparison circuit is configured to provide comparison outputs each based on a comparison of the output of the signal path combiner with a different one of the delayed signals;
• generating multiple test patterns using an Automatic Test Pattern Generation (ATPG) software tool, wherein each of the test patterns is configured to cause the delay circuit to apply one of the different respective delays;
• operating Automatic Test Equipment (ATE) to scan the test patterns into the semiconductor IC so as to operate the timing margin measurement sensor, such that:
• the delay circuit applies, at the different times, the different respective delays to the signal received at the input of the delay circuit, to provide, at the output of the delay circuit, the different delayed signals respective of the different delays, and
• the comparison circuit provides the comparison outputs each based on the comparison of the output of the signal path combiner with the different one of the delayed signals;
• and
• operating the ATE to scan out an output of the timing margin measurement sensor from the semiconductor IC, so as to measure, based on the comparison outputs and their associated different delays, a timing margin of at least one of the parallel bit paths,
• wherein the output of the timing margin measurement sensor comprises the comparison outputs of the comparison circuit.

Automatic Test Equipment (ATE) configured to test a semiconductor integrated circuit (IC) by:

• connecting to a semiconductor IC that comprises a timing margin measurement sensor, wherein the timing margin measurement sensor comprises:
• (i) a signal path combiner comprising:
• (a) a plurality of input paths, each connected to an input of a flip-flop of multiple flip-flops that are comprised in parallel bit paths of a data source in the IC, wherein each of the parallel bit paths terminates with a different one of the multiple flip-flops, and (b) an output,
• wherein the signal path combiner is configured such that each signal received on a different one of the flip-flops of the data source is also received by a respective one of the plurality of input paths of the signal path combiner;
• (ii) a delay circuit comprising:
• (a) an output, and (b) an input connected to the signal path combiner output,
• wherein the delay circuit is configured to apply, at different times, different respective delays to a signal received at the input of the delay circuit, to provide, at the output of the delay circuit, different delayed signals respective of the different delays;
• and
• (iii) a comparison circuit connected to:
• (a) the output of the delay circuit, and (b) the output of the signal path combiner,
• wherein the comparison circuit is configured to provide comparison outputs each based on a comparison of the output of the signal path combiner with a different one of the delayed signals;
• receiving multiple test patterns that were generated using an Automatic Test Pattern Generation (ATPG) software tool, wherein each of the test patterns is configured to cause the delay circuit to apply one of the different respective delays;
• scanning the test patterns into the semiconductor IC so as to operate the timing margin measurement sensor, such that:
• the delay circuit applies, at the different times, the different respective delays to the signal received at the input of the delay circuit, to provide, at the output of the delay circuit, the different delayed signals respective of the different delays, and
• the comparison circuit provides the comparison outputs each based on the comparison of the output of the signal path combiner with the different one of the delayed signals;
• and
• scanning out an output of the timing margin measurement sensor from the semiconductor IC, so at to measure, based on the comparison outputs and their associated different delays, a timing margin of at least one of the parallel bit paths,
• wherein the output of the timing margin measurement sensor comprises the comparison outputs of the comparison circuit.