Wrapper cell design and built-in self-test architecture for 3DIC test and diagnosis
AssigneeTaiwan Semiconductor Manufacturing Company, Ltd.
InventorsAnshuman Chandra, Sandeep Kumar Goel
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Abstract
Systems, methods, and devices are described herein for performing intra-die and inter-die tests of one or more dies of an integrated circuit. A cell of an integrated circuit includes a data register, an I/O pad, and a first multiplexer. The data register is configured to output a signal. The I/O pad is coupled to the data register and configured to receive and buffer the signal. The first multiplexer is coupled to the I/O pad and the data register. The multiplexer is configured to selectively output either the buffered signal or the signal based on whether a scan mode or a functional mode is enabled.
Claims20
A cell of an integrated circuit, the cell comprising:
- a first multiplexer coupled to an input/output (I/O) pad and a data register, the first multiplexer configured to selectively output either a signal from the data register or the buffered signal from the I/O pad based on whether a scan mode or a functional mode is enabled;
- and
- a logic gate coupled to an output from the first multiplexer, the logic gate configured to either toggle data or hold data provided to the data register.
An integrated circuit with built-in self-test (BIST) functionality, the integrated circuit comprising:
- a first die comprising a first cell comprising a first multiplexer, a first data register, and a first input/output (I/O) pad;
- and
- a second die comprising a second cell comprising a second multiplexer, a second data register, and a second I/O pad, wherein the first die is coupled to the second die via an inter-die interconnection.
A method of testing one or more dies using built-in self-test (BIST) functionality, the method comprising:
- receiving, by a data register of a die, data comprising a pre-determined test pattern;
- and
- providing, via a loop back path formed by an input/output (I/O) pad and a multiplexer, the buffered pre-determined test pattern back to the data register via a logic gate.
Dependencies are inferred from the claim text.