US 2026/0243822 A1 · SELECT GATE SCAN USING DOUBLE VERIFY

Abstract

A system and method are provided for retiring blocks in a memory device. The system and method perform a first select gate (SG) scan operation on a memory portion of a memory device. After performing the first SG scan operation, the system and method selectively perform a second SG scan operation on the memory portion, the second SG scan operation having different verification operations than the first SG scan operation. The system and method selectively perform one or more SG maintenance operations on the memory portion based on a result of performing at least one of the first SG scan operation and the second SG scan operation on the memory portion.

Claims20

Dependent claims

A system comprising:

a memory device;
and
a processing device, operatively coupled to the memory device, configured to perform operations comprising:
performing a first select gate (SG) scan operation on a memory portion of the memory device;
after performing the first SG scan operation, selectively performing a second SG scan operation on the memory portion, the second SG scan operation having different verification operations than the first SG scan operation;
and
selectively performing one or more SG maintenance operations on the memory portion based on a result of performing at least one of the first SG scan operation and the second SG scan operation on the memory portion.

4 more elements

Dependencies are inferred from the claim text.

Select gate scan using double verify

Life of this patent

Select gate scan using double verify

Life of this patent

Abstract

Claims20