G01R 31/318536
Scan chain arrangements
Official title: {Scan chain arrangements, e.g. connections, test bus, analog signals}
G01R31/318536 (Scan chain arrangements) appears on 1,147 US grants and 983 published applications in this corpus.
Search patents in G01R- Granted patents
- 1,147
- Published applications
- 983
- Assignees
- 247
- Inventors
- 1,449
- Latest grant
- 25 Aug 2026
Filings by year
| Year | Granted patents | Published applications |
|---|---|---|
| 1977 | 1 | 0 |
| 1978 | 0 | 0 |
| 1979 | 0 | 0 |
| 1980 | 0 | 0 |
| 1981 | 0 | 0 |
| 1982 | 2 | 0 |
| 1983 | 1 | 0 |
| 1984 | 3 | 0 |
| 1985 | 1 | 0 |
| 1986 | 1 | 0 |
| 1987 | 2 | 0 |
| 1988 | 5 | 0 |
| 1989 | 4 | 0 |
| 1990 | 10 | 0 |
| 1991 | 7 | 0 |
| 1992 | 8 | 0 |
| 1993 | 3 | 0 |
| 1994 | 9 | 0 |
| 1995 | 7 | 0 |
| 1996 | 30 | 0 |
| 1997 | 20 | 0 |
| 1998 | 19 | 0 |
| 1999 | 16 | 0 |
| 2000 | 14 | 0 |
| 2001 | 26 | 7 |
| 2002 | 16 | 26 |
| 2003 | 25 | 26 |
| 2004 | 28 | 35 |
| 2005 | 23 | 49 |
| 2006 | 32 | 36 |
| 2007 | 37 | 49 |
| 2008 | 36 | 52 |
| 2009 | 44 | 50 |
| 2010 | 62 | 55 |
| 2011 | 68 | 39 |
| 2012 | 43 | 38 |
| 2013 | 43 | 49 |
| 2014 | 55 | 55 |
| 2015 | 54 | 57 |
| 2016 | 56 | 47 |
| 2017 | 47 | 37 |
| 2018 | 37 | 34 |
| 2019 | 33 | 29 |
| 2020 | 26 | 25 |
| 2021 | 29 | 33 |
| 2022 | 36 | 30 |
| 2023 | 37 | 39 |
| 2024 | 44 | 41 |
| 2025 | 30 | 25 |
| 2026 | 17 | 20 |
By publication year. Applications have been published since 2001. 2026 runs to 8 Oct.
Subgroups
Granted patents
Recent patents
- Integrated circuit including constant-0 flip flops reconfigured to provide observable and controllable test points25 Aug 2026US 12,716,944 B2QUALCOMM Incorporated
- Path margin monitoring28 Jul 2026US 12,694,179 B1Synopsys, Inc.
- Wrapper cell design and built-in self-test architecture for 3DIC test and diagnosis21 Jul 2026US 12,687,578 B2Taiwan Semiconductor Manufacturing Company.Ltd
- Architecture for testing multiple scan chains30 Jun 2026US 12,669,541 B2STMicroelectronics International N. V.
- Integrated-circuit chip for retention cell testing23 Jun 2026US 12,663,469 B2Nordic Semiconductor ASA
- Wrapper Cell Design and Built-In Self-Test Architecture for 3DIC Test and Diagnosis8 Oct 2026US 2026/0309778 A1Taiwan Semiconductor Manufacturing Company.Ltd
- Efficient scannable register file cell with low overhead3 Sep 2026US 2026/0259262 A1International Business Machines Corporation
- Scan Operation Methods and Devices27 Aug 2026US 2026/0251708 A1Arm Limited
- Clock gating based on care bits in scan chains for reduced clock power during scan automatic test pattern generation13 Aug 2026US 2026/0235674 A1
- Semiconductor device and method of inspecting semiconductor device13 Aug 2026US 2026/0235675 A1Canon Kabushiki Kaisha
Most cited
By later US patents
- Emulation devices, systems and methods utilizing state machines263US 5,329,471 ATexas Instruments Incorporated · 1994
- Series maxium/minimum function computing devices, systems and methods238US 5,072,418 ATexas Instruments Incorporated · 1991
- Structure and method for producing mask-programmed integrated circuits which are pin compatible substitutes for memory-configured logic arrays223US 5,068,603 AXilinx, Inc. · 1991
- Microcontroller provided with hardware for supporting debugging as based on boundary scan standard-type extensions210US 5,590,354 AU. S. Philips Corporation · 1996
- Devices and method for generating and using systems, software waitstates on address boundaries in data processing197US 5,155,812 ATexas Instruments Incorporated · 1992