Devices and method for generating and using systems, software waitstates on address boundaries in data processing

A data processing device for use with banks of memory having a memory space divisible by memory pages, the data processing device comprising:

• a digital processor and an address bus and a data bus for connecting the digital processor to the banks of memory;
• storing means, connected to the digital processor, addressable by said digital processor, said digital processor including means for entering values into said storing means defining respective numbers of wait states corresponding to the memory pages;
• and
• wait state generator means connected to the address bus for generating the number of wait states defined by a value in said storing means for a particular memory page when an address is asserted by the digital processor on the particular memory page.

A data processing device, comprising:

• a digital processor;
• a plurality of peripheral devices coupled to said digital processor, the peripheral devices having addresses addressable by said digital processor, said peripheral devices having different operating speeds for communication with said digital processor;
• and
• said digital processor having a higher maximum speed than at least one of said peripheral devices, and said processor including programmable means for generating wait states in response to the asserted addresses of the peripheral devices to accommodate the speed of each slower peripheral device on an individual basis.

A method of operating a data processing device with peripheral devices having addresses and differing communication response periods, the method comprising the steps of:

• programming addressable registers of a data processing device to hold values representative of distinct numbers of wait states corresponding to different address ranges;
• selecting different ones of the peripheral devices by asserting addresses of each selected peripheral device;
• and
• generating a number of wait states, in response to an asserted address to a peripheral device and in response to the value held in one of the programmable registers that corresponds to the address range of the peripheral device, thereby accommodating the data processing device to the differing communication response periods of the peripheral devices.