G01R 31/318538
Topological or mechanical aspects
Official title: {Topological or mechanical aspects}
G01R31/318538 (Topological or mechanical aspects) appears on 138 US grants and 126 published applications in this corpus.
Search patents in G01R- Granted patents
- 138
- Published applications
- 126
- Assignees
- 53
- Inventors
- 186
- Latest grant
- 25 Aug 2026
Filings by year
| Year | Granted patents | Published applications |
|---|---|---|
| 1988 | 1 | 0 |
| 1989 | 0 | 0 |
| 1990 | 2 | 0 |
| 1991 | 2 | 0 |
| 1992 | 1 | 0 |
| 1993 | 0 | 0 |
| 1994 | 1 | 0 |
| 1995 | 1 | 0 |
| 1996 | 4 | 0 |
| 1997 | 1 | 0 |
| 1998 | 0 | 0 |
| 1999 | 4 | 0 |
| 2000 | 1 | 0 |
| 2001 | 0 | 1 |
| 2002 | 3 | 3 |
| 2003 | 2 | 1 |
| 2004 | 3 | 5 |
| 2005 | 0 | 4 |
| 2006 | 3 | 2 |
| 2007 | 3 | 1 |
| 2008 | 4 | 3 |
| 2009 | 1 | 3 |
| 2010 | 2 | 7 |
| 2011 | 7 | 2 |
| 2012 | 3 | 6 |
| 2013 | 4 | 6 |
| 2014 | 8 | 3 |
| 2015 | 7 | 11 |
| 2016 | 9 | 13 |
| 2017 | 11 | 8 |
| 2018 | 7 | 6 |
| 2019 | 6 | 7 |
| 2020 | 7 | 5 |
| 2021 | 5 | 7 |
| 2022 | 6 | 5 |
| 2023 | 5 | 5 |
| 2024 | 7 | 6 |
| 2025 | 6 | 6 |
| 2026 | 1 | 0 |
By publication year. Applications have been published since 2001. 2026 runs to 8 Oct.
Recent patents
- Integrated circuit including constant-0 flip flops reconfigured to provide observable and controllable test points25 Aug 2026US 12,716,944 B2QUALCOMM Incorporated
- Scan test in a single-wire bus circuit11 Nov 2025US 12,467,972 B2Qorvo US, Inc.
- Integrated circuit package for scan testing semiconductor chip, operating method of integrated circuit package, and integrated circuit9 Sep 2025US 12,411,175 B2Samsung Electronics Co., Ltd.
- Scan architecture for interconnect testing in 3D integrated circuits12 Aug 2025US 12,385,973 B2Taiwan Semiconductor Manufacturing Company.Ltd
- Testing interposer method and apparatus5 Aug 2025US 12,379,393 B2Texas Instruments Incorporated
- Scan architecture for interconnect testing in 3d integrated circuits20 Nov 2025US 2025/0355043 A1Taiwan Semiconductor Manufacturing Company.Ltd
- Test circuit in die stack13 Nov 2025US 2025/0347716 A1
- Test time reduction in circuits with redundancy flip-flops27 Mar 2025US 2025/0102574 A1STMicroelectronics International N. V.
- Scan testable through silicon vias13 Mar 2025US 2025/0087539 A1Texas Instruments Incorporated
- Partial chain reconfiguration for test time reduction27 Feb 2025US 2025/0067803 A1STMicroelectronics International N. V.
Most cited
By later US patents
- Interconnect substrate with circuits for field-programmability and testing of multichip modules and hybrid circuits80US 5,371,390 AAptix Corporation · 1994
- Semiconductor integrated circuit device having test control circuit in input/output area67US 5,509,019 AFujitsu Limited · 1996
- Flexible VLSI on-chip maintenance and test system with unit I/O cell design64US 4,912,709 AControl Data Corporation · 1990
- Interconnect structure with programmable IC for interconnecting electronic components, including circuitry for controlling programmable IC59US 5,654,564 AAptix Corporation · 1997
- Interconnect substrate with circuits for field-programmability and testing of multichip modules and hybrid circuits46US 5,973,340 AAptix Corporation · 1999