Integrated circuit package for scan testing semiconductor chip, operating method of integrated circuit package, and integrated circuit

An operating method of an integrated circuit package for scan testing a semiconductor chip, the operating method comprising:

• receiving a first input signal through a first input pad;
• receiving a selection signal by a selection signal circuit;
• determining, based on the selection signal, whether the first input signal is provided to one of a first test circuit and a second test circuit of at least one chip exposed to the semiconductor chip;
• and
• outputting a first output signal generated by the first test circuit or a second output signal generated by the second test circuit, wherein
• the outputting the first output signal or the second output signal comprises,
• when the first input signal is input to the first test circuit, outputting the first output signal to a first output pad exposed to outside of the semiconductor chip.

An integrated circuit for scan testing a semiconductor chip, the integrated circuit comprising:

• a first test circuit configured to receive one of a first input signal and a second input signal, and generate a first output signal;
• a second test circuit configured to receive the first input signal and generate a second output signal, wherein
• the first test circuit comprises
• a first decompressor configured to receive the first input signal or the second input signal,
• a first compressor configured to generate the first output signal, and
• a scan chain configured to connect the first decompressor with the first compressor, and
• the second test circuit comprises
• a second decompressor configured to receive the first input signal,
• a second compressor configured to generate the second output signal, and
• the scan chain configured to connect the second decompressor with the second compressor,
• a signal selection circuit configured to determine whether the first input signal or the second input signal is used in the first test circuit, based on a selection signal, and
• an output selection circuit configured to receive the first output signal from the first compressor and the second output signal from the second compressor, and output one of the first output signal and the second output signal based on the selection signal.