Flexible VLSI on-chip maintenance and test system with unit I/O cell design

A VLSI circuit having a built-in test and maintenance system and wherein essentially all of the signal outputs and outputs go unit I/O cells, comprising:

• an output buffer means, connected to provide output from the on-chip circuits to chip pins;
• an input buffer means, connected to provide input from chip pins to the on-chip circuits;
• an output register and a core logic, wherein the output buffer is connected to selectively receive input either from said output register or directly from said core logic;
• a control register, wherein said selectivity is controlled by signals supplied by said control register, said control register having only one data input from a pin;
• and
• a system clock input separated so as to be provided as a CLK 2 signal to the input register and the output register, and as a CLK 1 signal to the control register, and a disablement means provided to selectively disable the CLK 2 signal to allow the control register to be clocked without clocking either the input register or the output register.

A VLSI circuit having a built-in test and maintenance system and wherein essentially all of the signal inputs and outputs go through unit I/O cells, comprising:

• an output buffer means, connected to provide output from the on-chip circuits to chip pins;
• an input buffer means, connected to provide input from chip pins to the on-chip circuits;
• and
• at least one signal registration means having at least two outputs, and adapted to receive a mode select signal from off-chip and configured to pass said mode select signal with clocking on one of said outputs and earlier, without clocking, on the other output.

A VLSI circuit having a built-in test and maintenance system and wherein essentially all of the signal inputs and outputs go through unit I/O cells, comprising:

• an output buffer means, connected to provide output from the on-chip circuits to chip pins;
• an input buffer means, connected to provide input from chip pins to the on-chip circuits;
• and
• at least one signal registration means having at least two outputs, and adapted to receive a test enable signal from off-chip, said registration means being configured to pass said test enable signal with clocking on one of said outputs and earlier, without clocking, on the other output.

A VLSI circuit having a built-in test and maintenance system wherein essentially all of the signal inputs and outputs go through unit I/O cells, comprising:

• an output buffer means, connected to provide output from the on-chip circuits to chip pins;
• and input buffer means, connected to provide input from chip pins to the on-chip circuits;
• and
• a system clock input separated so as to be provided as a CLK 2 signal to the input register and the output register, and as a CLK 1 signal to the control register, and wherein a disablement means is provided to selectively disable the CLK 1 signal to allow the input and output registers to be serially loaded and unloaded without affecting the control register.

A VLSI circuit having a built-in test and maintenance system wherein essentially all of the signal inputs and outputs go through unit I/O cells, comprising:

• an output buffer means, connected to provide output from the on-chip circuits to chip pins;
• and input buffer means, connected to provide input from chip pins to the on-chip circuits;
• and
• a test data output pin selectively connectable to serially provided data from the core logic area, such as data from a scan path, or from the test data input and these may be logically XORed with output from the output register, through a test data output register.

A VLSI circuit having a built-in test and maintenance system wherein essentially all of the signal inputs and outputs go through unit I/O cells, comprising:

• an output buffer means, connected to provide output from the on-chip circuits to chip pins;
• and input buffer means, connected to provide input from chip pins to the on-chip circuits;
• and
• an input register, a test data input register and a core logic, wherein a shared input pin provides data to the test data input register for serially providing input data to the core logic and identical data to the input register, such as data to a scan path.