Partial chain reconfiguration for test time reduction
AssigneeSTMicroelectronics International N.V.
InventorsSandeep Jain, Shalini Pathak
Life of this patent
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AssigneeSTMicroelectronics International N.V.
InventorsSandeep Jain, Shalini Pathak
Estimating the term…
According to an embodiment, a first aspect relates to a method for testing a scan chain. The method includes segmenting the scan chain into two or more segments; adding a respective multiplexer at end points of each segment, wherein each pair of sequential segment shares a common multiplexer in between; asserting a select signal at a select terminal of the multiplexers such that a relative position of the two or more segments is rearranged positionally in a rearranged scan chain; generating a test pattern to be communicated to an input terminal of the rearranged scan chain and observing a test result at an output of the rearranged scan chain; and determining a fault condition in the rearranged scan chain based on comparing the test result and an expected result.
A method for testing a scan chain, the method comprising:
A scan chain, comprising:
A test system, comprising:
Dependencies are inferred from the claim text.