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US 12,379,393 B2Granted
Testing interposer method and apparatus
AssigneeTexas Instruments Incorporated
InventorLee D. Whetsel
Life of this patent
Estimating the term…
Abstract
The disclosure describes a novel method and apparatus for improving silicon interposers to include test circuitry for testing stacked die mounted on the interposer. The improvement allows for the stacked die to be selectively tested by an external tester or by the test circuitry included in the interposer.
Claims20
An interposer comprising:
- a first face;
- a second face;
- test access port circuitry including a test data input coupled to the first face, a test clock input coupled to the first face, a test mode select input coupled to the first face, a test data output coupled to the first face, and control output;
- stimulus generator circuitry including a first input coupled to the control output of the test access port circuitry, wherein the stimulus generator circuitry further includes a stimulus output;
- and
- a first multiplexer including a first data input coupled to the first face, a second data input coupled to the stimulus output, a control input coupled to the control output of the test access port circuitry, and an output coupled to the second face.
3 more elements
An interposer comprising:
- a first face;
- a second face;
- test access port circuitry including a test data input coupled to the first face, a test clock input coupled to the first face, a test mode select input coupled to the first face, a test data output coupled to the first face, and control output;
- control generator circuitry including a first output, a second output, a third output, and an input coupled to the control output of the test access port circuitry;
- stimulus generator circuitry including a first input coupled to the control output of the test access port circuitry, a second input coupled to the first output of the control generator circuitry, and a stimulus output;
- response collector circuitry including a first input coupled to the control output of the test access port circuitry, a second input coupled to the second output of the control generator circuitry, and a third input coupled to the second face;
- a first multiplexer including a first data input coupled to the first face, a second data input coupled to the stimulus output, a control input coupled to the control output of the test access port circuitry, and an output coupled to the second face;
- and
- a second multiplexer including a first data input coupled to the first face, a second data input coupled to the third output of the control generator circuitry, a control input coupled to the control output of the test access port circuitry, and an output coupled to the second face.
6 more elements
A system comprising:
- a substrate;
- a die stack;
- and
- a redistribution layer including:
- a first surface coupled to the substrate and including a test data input (TDI), a test clock (TCK) input, a test mode select (TMS) input, a test data output (TDO), and a first data input;
- a second surface opposite the first surface, wherein the second surface includes a first output, and wherein the second surface is coupled to the die stack;
- test access port (TAP) circuitry coupled to the TDI, the TCK input, the TMS input, and the TDO;
- stimulus generator circuitry coupled to the TAP circuitry;
- and
- a first multiplexer coupled to the first data input, the TAP circuitry, the stimulus generator circuitry, and the first output.
7 more elements
Dependencies are inferred from the claim text.