Scan architecture for interconnect testing in 3d integrated circuits
AssigneeTaiwan Semiconductor Manufacturing Company, Ltd.
InventorsSandeep Kumar GOEL, Yun-Han LEE, Saman M. I. ADHAM, Marat GERSHOIG
Life of this patent
Estimating the term…
Abstract
A method of using a semiconductor device includes receiving a signal at a first latch of a first plurality of latches on a first die. The method further includes relaying the signal from the first latch to a second latch of a second plurality of latches on a second die electrically connected to the first die. The method further includes relaying the signal from the second latch to a third latch of the second plurality of latches. The method further includes relaying the signal from the third latch to a fourth latch of the first plurality of latches.
Claims20
A method of using a semiconductor device, the method comprising:
- receiving a signal at a first latch of a first plurality of latches on a first die;
- relaying the signal from the first latch to a second latch of a second plurality of latches on a second die electrically connected to the first die;
- relaying the signal from the second latch to a third latch of the second plurality of latches;
- and
- relaying the signal from the third latch to a fourth latch of the first plurality of latches.
A method of using a semiconductor device, the method comprising:
- receiving a signal at a first latch of a first plurality of latches on a first die;
- relaying the signal from the first latch to a second latch of a second plurality of latches on a second die electrically connected to the first die, wherein relaying the signal from the first latch to the second latch comprises relaying the signal through a first intermediate component;
- relaying the signal from the second latch to a third latch of the second plurality of latches, wherein relaying the signal from the second latch to the third latch comprises relaying the signal directly from the second latch to the third latch;
- and
- relaying the signal from the third latch to a fourth latch of the first plurality of latches.
A device comprising:
- a first plurality of latches in a first die;
- a second plurality of latches in a second die electrically connected to the first die;
- a first plurality of multiplexers in the first die, wherein a number of multiplexers of the first plurality of multiplexers is different from a number of latches of the first plurality of latches;
- and
- a second plurality of multiplexers in the second die, wherein a number of multiplexers of the second plurality of multiplexers is different from a number of latches of the second plurality of latches, and a corresponding multiplexer of the first plurality of multiplexer or the second plurality of multiplexers is electrically between each latch of the first plurality of latches and a corresponding latch of the second plurality of latches.
Dependencies are inferred from the claim text.