Semiconductor integrated circuit device having test control circuit in input/output area
AssigneeFujitsu Limited
InventorTakeshi Yamamura
Life of this patent
Estimating the term…
Abstract
A semiconductor integrated circuit includes a chip (10a), a core area (12) on the chip in which tester circuits (14) are placed, and an I/O area (13) on the chip. The I/O area is provided at the periphery of the core area, and in the I/O area a plurality of tester circuits (17) are placed for testing the functions of respectively testee circuits in, respectively core area. The I/O area is provided with test control circuits (15) for supplying a control signal (C2) and a clock signal (C3), for testing said tester circuits, to the test circuits and testee circuits, on the basis of an external control signal supplied from outside.
Claims26
A semiconductor integrated circuit device, comprising:
- a chip having at least first and second corner areas;
- a core area on said chip on which testee circuits having specific functions are placed;
- an I/O area on said chip located at a periphery of said core area;
- a plurality of tester circuits located in said I/O area, and and selectively connected to said testee circuits in said core area, for testing the functions of said testee circuits in said core area;
- and
- test control circuits located in said I/O area and connected to said testee circuits and said tester circuits, for supplying a test control signal and a test clock signal to said tester and testee circuits, for testing said testee circuits on the basis of an external control signal coming from outside.
A semiconductor integrated circuit device having defined thereon a core area and an I/O area located at a periphery of the core area, the I/O area having at least first and second corner portions, said semiconductor device comprising:
- a plurality of testee circuits located in the core area and having specific functions;
- a plurality of tester circuits located in the I/O area and selectively connected to said testee circuits in said core area, for testing the functions of said plurality of testee circuits in the core area;
- a test control decoding circuit located in the first corner portion of the I/O area, for decoding an external control signal and generating a test control signal so as to control the plurality of tester circuits;
- and
- a test control clock circuit located in the second corner portion of the I/O area, for generating a test clock signal based on the control signal generated by said test control decoding circuit.
Dependencies are inferred from the claim text.