Series maxium/minimum function computing devices, systems and methods

A data processing device, comprising:

• a data memory and a data bus connected to said data memory;
• arithmetic logic circuitry for electronically producing digital signals representing computed arithmetic values, the arithmetic values over time having a maximum value, said arithmetic logic circuitry having an output, a first input and a second input;
• an accumulator having an input connected to said output of said arithmetic logic circuitry and having an accumulator output connected to the first input of said arithmetic logic circuitry;
• an accumulator buffer connected to said accumulator for selective bidirectional transfers therebetween;
• and
• circuitry for selectively coupling said first input of said arithmetic logic circuitry to said accumulator buffer or to said data bus, said arithmetic logic circuitry responsive to an instruction for comparing the contents of said accumulator via said first input with the contents of said accumulator buffer via said second input and then transferring a value in the accumulator to said accumulator buffer when a value in said accumulator buffer is less than the value in the accumulator.

A signal processing system comprising:

• sensor means for producing a digital signal in response to a physical input representative of a pattern;
• a programmable microcomputer having an instruction decoder, a first register and a second register, and arithmetic logic unit means for computing an arithmetic difference between a first value representative of the digital signal in the first register and a second value in the second register and then storing in response to said instruction decoder the first value into the second register or the second value into the first register thereby computing a maximum or minimum value of the signal depending on the arithmetic difference and on an instruction type;
• and
• a program memory connected to said microcomputer holding instructions for execution by said microcomputer to recognize the pattern.

A data processing apparatus comprising:

• an arithmetic logic unit having first and second data inputs and an output;
• a first register connected to the first data input and to the output of said arithmetic logic unit;
• and
• a second register connected between said first register and the second input of said arithmetic logic unit, wherein a signal from said arithmetic logic unit determined from a signal of a difference in value between said firs register and said second register selectively stores to said second register a value from said first register depending on whether the value in said first register is greater or lesser than a value in said second register.

A data processing system comprising:

• an input device operative to produce a digital signal in response to a physical input representative of a pattern;
• a computer device connected to said input device having;
• an arithmetic logic unit having first and second data inputs and an output;
• a first register connected to the first data input and to the output of said arithmetic logic unit;
• and
• a second register connected between said first register and the second input of said arithmetic logic unit, wherein a signal from said arithmetic logic unit determined from a difference in value between said first register and said second register stores to said second register a value from said first register;
• and
• an output device connected to said computing device.