G01R 31/318583
Design for test
Official title: {Design for test}
G01R31/318583 (Design for test) appears on 502 US grants and 372 published applications in this corpus.
Search patents in G01R- Granted patents
- 502
- Published applications
- 372
- Assignees
- 180
- Inventors
- 908
- Latest grant
- 25 Aug 2026
Filings by year
| Year | Granted patents | Published applications |
|---|---|---|
| 1981 | 2 | 0 |
| 1982 | 0 | 0 |
| 1983 | 0 | 0 |
| 1984 | 0 | 0 |
| 1985 | 2 | 0 |
| 1986 | 0 | 0 |
| 1987 | 0 | 0 |
| 1988 | 1 | 0 |
| 1989 | 0 | 0 |
| 1990 | 1 | 0 |
| 1991 | 3 | 0 |
| 1992 | 4 | 0 |
| 1993 | 4 | 0 |
| 1994 | 4 | 0 |
| 1995 | 7 | 0 |
| 1996 | 15 | 0 |
| 1997 | 12 | 0 |
| 1998 | 16 | 0 |
| 1999 | 7 | 0 |
| 2000 | 13 | 0 |
| 2001 | 18 | 4 |
| 2002 | 13 | 10 |
| 2003 | 17 | 16 |
| 2004 | 9 | 25 |
| 2005 | 7 | 18 |
| 2006 | 17 | 17 |
| 2007 | 20 | 9 |
| 2008 | 16 | 15 |
| 2009 | 17 | 14 |
| 2010 | 16 | 12 |
| 2011 | 18 | 10 |
| 2012 | 10 | 14 |
| 2013 | 12 | 13 |
| 2014 | 16 | 15 |
| 2015 | 19 | 17 |
| 2016 | 15 | 16 |
| 2017 | 24 | 21 |
| 2018 | 16 | 14 |
| 2019 | 18 | 19 |
| 2020 | 17 | 14 |
| 2021 | 21 | 17 |
| 2022 | 15 | 13 |
| 2023 | 19 | 16 |
| 2024 | 19 | 20 |
| 2025 | 15 | 8 |
| 2026 | 7 | 5 |
By publication year. Applications have been published since 2001. 2026 runs to 8 Oct.
Subgroups
Granted patents
Recent patents
- Secure scan testing of integrated circuits25 Aug 2026US 12,716,945 B2SK hynix Inc.
- Integrated circuit with multiplexer for testing16 Jun 2026US 12,656,397 B2Samsung Electronics Co., Ltd.
- Methods and apparatus to identify faults in processors12 May 2026US 12,625,179 B2Texas Instruments Incorporated
- Scan cell placing method and scan cell placing apparatus21 Apr 2026US 12,607,979 B2UIF (University Industry Foundation), Yonsei University
- Circuitry including scan and non-scan registers14 Apr 2026US 12,601,784 B2Arm Limited
- Secure scan testing of integrated circuits28 May 2026US 2026/0147041 A1SK hynix Inc.
- Debug system and method for operating a debug system19 Mar 2026US 2026/0079205 A1PUFsecurity Corporation
- Scan Test Security for Semiconductor Devices5 Mar 2026US 2026/0063714 A1NVIDIA Corporation
- Semiconductor integrated circuit22 Jan 2026US 2026/0023114 A1Rohm Co., Ltd.
- Power management cluster design system and method using a no-code approach8 Jan 2026US 2026/0009850 A1Itda Semiconductor Co., Ltd.
Most cited
By later US patents
- Method for manufacturing test simulation in electronic circuit design195US 5,539,652 AHewlett-Packard Company · 1996
- Method and apparatus for performing fully visible tracing of an emulation116US 5,754,827 AMentor Graphics Corporation · 1998
- JTAG interface system for communicating with compliant and non-compliant JTAG devices110US 5,708,773 AUnisys Corporation · 1998
- Constraint driven insertion of scan logic for implementing design for test within an integrated circuit design98US 5,903,466 ASynopsys, Inc. · 1999
- Integrated circuits carrying intellectual property cores and test ports92US 6,643,810 B2Texas Instruments Incorporated · 2003