Method and apparatus for performing fully visible tracing of an emulation

An apparatus comprising:

• a plurality of field programmable gate arrays (FPGAs) for emulating a circuit design, each field programmable gate array being a single integrated circuit comprising both a plurality of combinatorial logic blocks (LEs) for realizing circuit elements of the circuit design and a first on-chip integrated debugging facility for outputting signal state values of the LEs on a clock cycle by clock cycle basis;
• and
• trace memory coupled to the FPGAs comprising a plurality of memory locations for capturing and storing the LE signal state values output in a deterministic locality topology, under which the relative memory location within a clock cycle of LE signal state values where the signal state value of a particular LE is stored is predeterminable.

In an emulation system, a method for performing fully visible tracing of an emulation, the method comprising the steps of:

• a) outputting signal state values for all logic elements (LEs) of each field programmable gate array (FPGA) of the emulation system used for emulating a circuit design;
• b) capturing and storing the LE signal state values output into memory locations of a trace memory in a deterministic locality topology, under which the relative memory location within a block of memory locations used for storing a clock cycle of signal state values where the signal state value of a LE is stored is predeterminable.

A computer system comprising means for compiling and mapping a circuit design to logic elements (LE) of an emulation system including means for generating a cross reference file for cross referencing circuit elements of the circuit design to relative memory locations within a block of memory locations of a trace memory used to store a clock cycle of signal state values of the LEs where the signal state values of the LEs onto which the circuit elements are mapped are stored, the emulation system being equipped to capture and store signal state values of all LEs in the trace memory on a clock cycle by clock cycle basis, employing a deterministic locality topology.

In a computer system, a method for compiling and mapping a circuit design to logic elements (LE) of an emulation system, the method comprising the step of generating a cross reference file for cross referencing circuit elements of the circuit design to relative memory locations within a block of memory locations of a trace memory used to store a clock cycle of signal state values of the LEs where the signal state values of the LEs onto which the circuit elements are mapped are stored, the emulation system being equipped to capture and store signal state values of all LEs in the trace memory on a clock cycle by clock cycle basis, employing a deterministic locality topology.