Methods and apparatus to identify faults in processors

A non-transitory computer readable medium storing program instructions that, when executed by one or more processors, cause the one or more processors to:

• cause execution of instructions to modify contents of a set of memory circuits of a device under test (DUT);
• determine a set of positions of a time window;
• determine a number of observable modifications of the contents of the set of memory circuits in the time window for each of the set of positions;
• and
• determine a first position out of the set of positions at which the time window provides the greatest number of observable modifications.

A system, comprising:

• first circuitry configured to:
• cause performance of a first test on a device under test (DUT) to modify contents of a set of memory circuits of the DUT;
• cause performance of a second test on the DUT, wherein the second test is a partial portion of the first test, and wherein at least one modification of the contents of the set of memory circuits is observable during the second test but unobservable after the first test;
• and
• provide the contents of the set of memory circuits from the second test for detection of a fault in the DUT.