Scan cell placing method and scan cell placing apparatus
AssigneeUIF (University Industry Foundation), Yonsei University
InventorsSungho Kang, Sang Jun Lee
Life of this patent
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Abstract
There is provided a scan cell placing method including calculating a weight of each scan cell from a deterministic pattern input to a plurality of scan cells, dividing the scan cells into a coverage group and a power group on the basis of the weights, forming a plurality of power subgroups from a result of providing a pseudo random pattern to scan cells belonging to the power group, and scheduling one or more of the power subgroups to reduce peak power in a test process.
Claims24
A scan cell placing method comprising:
- calculating a weight of each scan cell from a deterministic pattern input to a plurality of scan cells;
- dividing the scan cells into a coverage group and a power group according to the weight;
- forming a plurality of power subgroups from a result of providing a pseudo random pattern to scan cells belonging to the power group;
- and
- scheduling one or more of the power subgroups to reduce peak power in a test process,
- wherein the calculating of the weight comprises calculating a weight by dividing the number of first-logic state bits included in a deterministic test pattern provided to the scan cell by a value obtained by subtracting the number of first-logic state bits included in the deterministic test pattern provided to the scan cell from the sum of the number of the first logic state bits and the number of second logic state bits complementary to the first logic state bits.
A scan cell placing apparatus for placing scan cells on which a built-in self-test of a semiconductor circuit is performed, the apparatus comprising:
- at least one processor;
- and
- a memory storing one or more programs executable by the at least one processor,
- wherein, when the one or more programs are executed by the at least one processor, the at least one processor performs a test method,
- wherein the test method comprises:
- calculating a weight of each scan cell from a deterministic pattern input to a plurality of scan cells;
- dividing the plurality of scan cells into a coverage group and a power group according to the weights;
- forming a plurality of power subgroups from a result of providing a pseudo random pattern to scan cells belonging to the power group;
- and
- rearranging one or more of the plurality of power subgroups to reduce peak power in a test process,
- wherein the calculating of the weight comprises calculating a weight by dividing the number of first logic state bits included in a deterministic test pattern provided to the scan cell by a value obtained by subtracting the number of first logic state bits from the sum of the number of the first logic state bits and the number of second logic state bits complementary to the first logic state bits.
Dependencies are inferred from the claim text.