Constraint driven insertion of scan logic for implementing design for test within an integrated circuit design

In a computer implemented circuit synthesis system, a method of optimizing a netlist to a set of constraints, said method comprising the steps of:

• receiving a netlist comprising scannable and non-scan sequential cells, said netlist defining a design;
• replacing said non-scan sequential cells with scannable sequential cells;
• determining scan chains of said scannable sequential cells for application of test vectors to combinational logic of said design;
• routing connections between scannable sequential cells to form said scan chains in said netlist;
• and
• performing a low effort optimization by performing a size design optimization on said netlist to satisfy performance constraints, said size design optimization performed only on a portion of said netlist along critical points wherein said portion includes only scannable sequential cells and other design elements added for design for test.

In a computer implemented circuit synthesis system, a method of optimizing a design to a set of constraints, said design represented as a netlist including scannable sequential cells, said method comprising the steps of:

• determining scan chains of said scannable sequential cells for application of test vectors to combinational logic;
• implementing said scan chains in said netlist by forming links between scannable sequential cells;
• performing a low effort optimization to satisfy performance constraints by performing a first set of optimization procedures only on a portion of said design along critical points wherein said portion comprises only scannable sequential cells and other design elements added for design for test;
• selectively performing a medium effort optimization by performing said low effort optimization and further applying said first set of optimization procedures to said netlist along critical paths across all said design;
• and
• selectively performing a high effort optimization by performing said medium effort optimization and further applying sequential mapping to said design across critical points and by applying a size down procedure to said design across noncritical points.

A system for optimizing a design to a set of constraints, said design represented as a netlist including scannable sequential cells, said system having a processor coupled to a memory unit wherein said processor is programmed to perform logic processing, said system further comprising:

• determining logic determining scan chains of said scannable sequential cells for applying test vectors to said design;
• scan chain logic implementing said scan chains in said netlist by providing connections between scannable sequential cells;
• first optimization logic performing a low effort optimization in order to satisfy performance constraints by applying size design optimizations only to a portion of said netlist along critical points wherein said portion comprises only scannable sequential cells and other design elements added for design for test;
• and
• second optimization logic selectively performing a medium effort optimization by applying said size design optimizations to all of said netlist along critical paths.