US 2026/0079205 A1Published application

Debug system and method for operating a debug system

AssigneePUFsecurity Corporation

InventorsCHING-WEN HSU, CHIA-CHO WU

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Abstract

The present application discloses a debug system. The debug system includes a DTM, a first DM, a second DM, and a module selector. The first DM is coupled to a first processing core, and the second DM is coupled to a second processing core. The module selector is coupled to the DTM, the first DM, and the second DM. When a selection data register of the DTM is written with a first value, the DTM controls the module selector to select a first path coupled between the DTM and the first DM so as to access the first processing core through the first path. When the selection data register is written with a second value, the DTM controls the module selector to select a second path coupled between the DTM and the second DM so as to access the second processing core through the second path.

Claims18

Dependent claims

A debug system comprising:

a debug transport module (DTM) configured to receive commands from a debugger for performing debug operations upon a plurality of processing cores of a hardware platform;
and
a first debug module (DM) coupled to at least one first processing core of the hardware platform;
a second DM coupled to at least one second processing core of the hardware platform;
and
a module selector coupled to the DTM, the first DM, and the second DM, and configured to select at least from a first path coupled between the DTM and the first DM and a second path coupled between the DTM and the second DM;
wherein the DTM comprises a selection data register coupled to a control terminal of the module selector through a pin of the DTM, and the DTM is further configured to, when the selection data register is written with a first value, control the module selector to select the first path so as to access the at least one first processing core through the first path and the first DM, and, when the selection data register is written with a second value different from the first value, control the module selector to select the second path so as to access the at least one second processing core through the second path and the second DM.

4 more elements

A method for operating a debug system to perform debug operations upon a plurality of processing cores of a hardware platform, wherein the debug system comprises a debug transport module (DTM), a first debug module (DM), a second DM, and a module selector, the first DM is coupled to at least one first processing core of the hardware platform, the second DM is coupled to at least one second processing core of the hardware platform, the module selector is coupled to the DTM, the first DM and the second DM, and the method comprising

when a selection data register of the DTM is written with a first value, the DTM controlling the module selector to select a first path coupled between the DTM and the first DM;
the DTM accessing the at least one first processing core through the first path and the first DM after the first path is selected;
when the selection data register is written with a second value different from the first value, the DTM controlling the module selector to select a second path coupled between the DTM and the second DM;
and
the DTM accessing the at least one second processing core through the second path and the second DM after the second path is selected.

2 more elements

Dependencies are inferred from the claim text.

Facts

Application: 19/329,075Filed 15 Sep 2025
Priority: 19 Sep 2024
Published: 19 Mar 2026
Term ends: Not estimatedThe source records don’t support an estimate.

Classification6 codes

G01R 31/318588
Design for test: security aspects
G01R 31/31705
Testing of digital circuits: debugging aspects, e.g. using test circuits for debugging, using dedicated debugging test circuits
G01R 31/318572
Using scanning techniques, e.g. LSSD, Boundary Scan, JTAG: input/Output interfaces
G06F 11/2242
To test CPU or processors: in multi-processor systems, e.g. one processor becoming the primary tester