Scan Test Security for Semiconductor Devices

A semiconductor device, comprising:

• a scan chain and a scan data output, wherein scan data bits may appear sequentially at the scan data output responsive to a scan clock when the device is in a scan mode;
• initial masking circuitry operable to obscure, responsive to the device transitioning from a non-scan mode to the scan mode, a first n bits of the scan data appearing at the scan data output and not to obscure n+1st and subsequent bits of the scan data appearing at the scan data output, wherein n corresponds to a length of the scan chain;
• infinite masking circuitry operable to obscure, responsive to an infinite masking trigger, all scan data bits appearing at the scan data output until a reset of the device occurs;
• monitoring and security enforcement circuitry operable to detect if a configuration of the device is being changed and to generate the infinite masking trigger if a detected configuration change corresponds to a potential security risk.