H10W 20/084
For dual-damascene structures
Official title: {for dual-damascene structures}
H10W20/084 (For dual-damascene structures) appears on 5,116 US grants and 5,306 published applications in this corpus.
Search patents in H10W- Granted patents
- 5,116
- Published applications
- 5,306
- Assignees
- 477
- Inventors
- 6,286
- Latest grant
- 6 Oct 2026
Filings by year
| Year | Granted patents | Published applications |
|---|---|---|
| 1984 | 1 | 0 |
| 1985 | 0 | 0 |
| 1986 | 0 | 0 |
| 1987 | 0 | 0 |
| 1988 | 2 | 0 |
| 1989 | 0 | 0 |
| 1990 | 0 | 0 |
| 1991 | 5 | 0 |
| 1992 | 5 | 0 |
| 1993 | 5 | 0 |
| 1994 | 2 | 0 |
| 1995 | 6 | 0 |
| 1996 | 5 | 0 |
| 1997 | 14 | 0 |
| 1998 | 30 | 0 |
| 1999 | 66 | 0 |
| 2000 | 141 | 0 |
| 2001 | 210 | 89 |
| 2002 | 274 | 278 |
| 2003 | 255 | 320 |
| 2004 | 290 | 357 |
| 2005 | 223 | 368 |
| 2006 | 237 | 289 |
| 2007 | 241 | 307 |
| 2008 | 201 | 243 |
| 2009 | 165 | 188 |
| 2010 | 177 | 159 |
| 2011 | 165 | 130 |
| 2012 | 120 | 132 |
| 2013 | 139 | 96 |
| 2014 | 153 | 148 |
| 2015 | 139 | 183 |
| 2016 | 189 | 173 |
| 2017 | 195 | 173 |
| 2018 | 164 | 183 |
| 2019 | 195 | 197 |
| 2020 | 213 | 241 |
| 2021 | 185 | 220 |
| 2022 | 150 | 216 |
| 2023 | 152 | 218 |
| 2024 | 149 | 162 |
| 2025 | 171 | 156 |
| 2026 | 82 | 80 |
By publication year. Applications have been published since 2001. 2026 runs to 8 Oct.
Subgroups
Granted patents
- H10W 20/085Involving intermediate temporary filling with material1,424
- H10W 20/087Involving multiple stacked pre-patterned masks970
- H10W 20/088Involving partial etching of via holes861
- H10W 20/086Involving buried masks519
- H10W 20/0886Involving forming a via in a via-level dielectric prior to deposition of250
- H10W 20/0888Wherein via-level dielectrics are compositionally different than trench-level dielectrics223
- H10W 20/0884Involving forming vias by burying sacrificial pillars in the dielectric parts and99
- H10W 20/0882Wherein the dual damascene structure is in a photoresist layer79
Recent patents
- Semiconductor structure and method for manufacturing same6 Oct 2026US 12,757,712 B2Changxin Memory Technologies, Inc.
- Through layer skip via6 Oct 2026US 12,757,713 B2International Business Machines Corporation
- Subtractive lines and vias with wrap-around contact15 Sep 2026US 12,740,394 B2International Business Machines Corporation
- Semiconductor package and method of fabricating semiconductor package15 Sep 2026US 12,740,446 B2Taiwan Semiconductor Manufacturing Company.Ltd
- Dual damascene fully-aligned via interconnects with dual etch layers8 Sep 2026US 12,733,472 B2International Business Machines Corporation
- Layer-by-layer formation of through-substrate via8 Oct 2026US 2026/0314369 A1Taiwan Semiconductor Manufacturing Company.Ltd
- Hybrid method for forming semiconductor interconnect structure8 Oct 2026US 2026/0314370 A1Taiwan Semiconductor Manufacturing Company.Ltd
- Integrated passive device and method for manufacturing the same, electronic apparatus8 Oct 2026US 2026/0314393 A1Beijing BOE Sensor Technology Co., Ltd.
- Semiconductor packages and methods for fabricating the same8 Oct 2026US 2026/0314446 A1Samsung Electronics Co., Ltd.
- Semiconductor device and method8 Oct 2026US 2026/0314458 A1Taiwan Semiconductor Manufacturing Company.Ltd
Most cited
By later US patents
- Method for depositing an amorphous carbon layer1,124US 6,573,030 B1APPLIED Materials.Inc. · 2003
- Production of elemental thin films using a boron-containing reducing agent809US 6,475,276 B1ASM Microchemistry Oy · 2002
- Process of vertically stacking multiple wafers supporting different active integrated circuit (IC) devices775US 7,157,787 B2Intel Corporation · 2007
- Plasma processes for depositing low dielectric constant films671US 6,303,523 B1APPLIED Materials.Inc. · 2001
- Method of making an edge seal for a semiconductor device581US 6,734,090 B2International Business Machines Corporation · 2004