Semiconductor package and method of fabricating semiconductor package
AssigneeTaiwan Semiconductor Manufacturing Company, Ltd.
InventorsWei-Ming Wang, Yu-Hung Lin, Shih-Peng Tai, Kuo-Chung Yee
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AssigneeTaiwan Semiconductor Manufacturing Company, Ltd.
InventorsWei-Ming Wang, Yu-Hung Lin, Shih-Peng Tai, Kuo-Chung Yee
Estimating the term…
A semiconductor package includes a substrate, a first die, a second die, a resistant layer, an encapsulant and an interlink structure. The first die has a first thickness larger than a second thickness of the second die. The resistant layer is disposed on the first and second dies and conformally covers the first and second dies. The encapsulant is disposed on the resistant layer and wraps around the first and second dies. The interlink structure is disposed above the first and second dies and embedded in the encapsulant, and the interlink structure is electrically connected with the first and second dies. The interlink structure includes a first via portion vertically extending through the encapsulant and connected to the first die, a second via portion extending vertically through the encapsulant and connected to the second die, and a routing line portion disposed on and connected with the first and second via portions, and the first via portion is shorter than the second via portion.
A semiconductor package, comprising:
A semiconductor package, comprising:
A semiconductor package, comprising:
Dependencies are inferred from the claim text.