Hybrid method for forming semiconductor interconnect structure

A semiconductor device, comprising:

• a substrate;
• a conductive feature disposed in a top portion of the substrate;
• a first dielectric layer disposed over the substrate;
• an etch stop layer disposed over the first dielectric layer;
• a second dielectric layer disposed over the etch stop layer;
• a first metal line disposed on the etch stop layer and within the second dielectric layer, the first metal line comprising a first metal and being separated from the conductive feature by the etch stop layer;
• and
• a second metal line comprising a second metal different from the first metal, the second metal line comprising a line portion disposed within the second dielectric layer and a via portion extending through the etch stop layer and the first dielectric layer to interface with the conductive feature,
• wherein the via portion is narrower than the line portion, and the first metal line is narrower than the line portion.

A semiconductor device, comprising:

• a substrate comprising an active region;
• a source/drain feature disposed in the active region;
• a metal gate stack disposed over the substrate and adjacent to the source/drain feature;
• an interlayer dielectric layer disposed over the substrate;
• a source/drain contact disposed in the interlayer dielectric layer and interfacing with the source/drain feature;
• an etch stop layer disposed over the interlayer dielectric layer;
• a dielectric layer disposed over the etch stop layer;
• a first metal line disposed on the etch stop layer and within the dielectric layer, the first metal line comprising a first metal;
• and
• a second metal line disposed within the dielectric layer and comprising a second metal different from the first metal, the second metal line being wider than the first metal line and extending through the etch stop layer and interfacing with the source/drain contact.