Process of vertically stacking multiple wafers supporting different active integrated circuit (IC) devices

A microelectronic package, comprising:

• a first die, the first die having a front side and a back side;
• a first tapered via formed in the first die through an active layer of the back side of the first wafer and an interlayer dielectric layer of the front side of the first wafer, the first tapered via having a larger face and a smaller face, the larger face located at the back side of the first die;
• a second die, the second die having a front side and a back side, the back side of the second die facing the back side of the first die;
• and
• a second tapered via formed in the second die, the second tapered via having a larger face and a smaller face, the larger face located at the back side of the second die and bonded to the larger face of the first tapered via.

A vertically stacked multiple wafer system, comprising:

• a first bonded wafer pair including a first wafer, a second wafer, and a first set of metallic lines formed in interlayer dielectrics on opposing surfaces of the first wafer and the second wafer, the first set of metallic lines bonding the first wafer to the second wafer and electrically connecting active devices of the first and second wafers;
• a second bonded wafer pair including a third wafer, a fourth wafer, and a second set of metallic lines formed in interlayer dielectrics on opposing surfaces of the third wafer and the fourth wafer, the second set of metallic lines bonding the third wafer to the fourth wafer and electrically connecting active devices of the third and fourth wafers;
• a first tapered via formed in the second wafer through an active layer of a back side of the second wafer and an interlayer dielectric layer of a front side of the second wafer, the first tapered via having a first end connected to a metallic line in the first set of metallic lines and a second end at the back side of the second wafer, the first end having a smaller area than the second end;
• and
• a second tapered via formed in the third wafer, the second tapered via having a third end at a back side of the third wafer and a fourth end connected to a metallic line in the second set of metallic lines, the third end having a larger area than the fourth end, wherein the third end of the second tapered via is bonded to the second end of the first tapered via to bond the first bonded wafer pair to the second bonded wafer pair.

A vertically stacked wafer system comprising:

• a first wafer comprising:
• a first front side having an interlayer dielectric layer;
• a first back side having an active layer;
• and
• a first via comprising a first section formed in the interlayer dielectric layer and a second section formed in the active layer, the second section having a horizontal cross-sectional area larger than a horizontal cross-sectional area of the first section;
• and
• a second wafer comprising:
• a second front side;
• a second back side facing the first back side of the first wafer;
• and
• a second via comprising a third section formed in the second back side and a fourth section formed in the second front side, wherein a surface of the third section is bonded to a surface of the second section bonding the first wafer to the second wafer.

A vertically stacked wafer system comprising:

• a first bonded wafer pair including a first wafer, a second wafer, and a first set of metallic lines formed in interlayer dielectrics on opposing surfaces of the first wafer and the second wafer, the first set of metallic lines bonding the first wafer to the second wafer and electrically connecting active devices of the first and second wafers;
• a second bonded wafer pair including a third wafer, a fourth wafer, and a second set of metallic lines formed in interlayer dielectrics on opposing surfaces of the third wafer and the fourth wafer, the second set of metallic lines bonding the third wafer to the fourth wafer and electrically connecting active devices of the third and fourth wafers;
• a first pair of bonded interwafer vias including:
• a first interwafer via formed in the second wafer, the first interwafer via having a first surface located at a back side of the second wafer, the first interwafer via extending through an active layer of the back side of the second wafer and an interlayer dielectric layer of a front side of the second wafer;
• and
• a second interwafer via formed in the third wafer, the second interwafer via having a second surface located at a back side of the third wafer, the second interwafer via extending through an active layer of the back side of the third wafer and an interlayer dielectric layer of a front side of the third wafer, the second surface of the second interwafer via bonded to the first surface of the first interwafer via;
• and
• a pair of bonded dummy vias including:
• a first dummy via having a third surface located at the back side of the second wafer, the first dummy via ending in the active layer of the back side of the second wafer;
• and
• a second dummy via having a fourth surface located at the back side of the third wafer, the second dummy via ending in the active layer of the back side of the third wafer, the fourth surface of the second dummy via bonded to the third surface of the first dummy via.