H10W 20/0882
Wherein the dual damascene structure is in a photoresist layer
Official title: {wherein the dual damascene structure is in a photoresist layer}
H10W20/0882 (Wherein the dual damascene structure is in a photoresist layer) appears on 79 US grants and 77 published applications in this corpus.
Search patents in H10W- Granted patents
- 79
- Published applications
- 77
- Assignees
- 37
- Inventors
- 175
- Latest grant
- 17 Feb 2026
Filings by year
| Year | Granted patents | Published applications |
|---|---|---|
| 1998 | 2 | 0 |
| 1999 | 5 | 0 |
| 2000 | 8 | 0 |
| 2001 | 5 | 0 |
| 2002 | 5 | 4 |
| 2003 | 4 | 3 |
| 2004 | 3 | 2 |
| 2005 | 1 | 0 |
| 2006 | 1 | 3 |
| 2007 | 0 | 4 |
| 2008 | 1 | 2 |
| 2009 | 0 | 3 |
| 2010 | 1 | 2 |
| 2011 | 2 | 3 |
| 2012 | 3 | 3 |
| 2013 | 3 | 3 |
| 2014 | 3 | 3 |
| 2015 | 3 | 4 |
| 2016 | 3 | 2 |
| 2017 | 2 | 1 |
| 2018 | 1 | 6 |
| 2019 | 3 | 4 |
| 2020 | 3 | 2 |
| 2021 | 2 | 2 |
| 2022 | 2 | 4 |
| 2023 | 3 | 9 |
| 2024 | 4 | 1 |
| 2025 | 5 | 7 |
| 2026 | 1 | 0 |
By publication year. Applications have been published since 2001. 2026 runs to 8 Oct.
Recent patents
- Method for fabricating a semiconductor device with a composite barrier structure17 Feb 2026US 12,557,622 B2Nanya Technology Corporation
- Semiconductor device with contact structure16 Sep 2025US 12,417,982 B2Nanya Technology Corporation
- Semiconductor device and method of forming an embedded redistribution layer8 Jul 2025US 12,354,990 B2STATS ChipPAC Pte. Ltd.
- Method for fabricating semiconductor device with chelating agent24 Jun 2025US 12,341,054 B2Nanya Technology Corporation
- Method for fabricating semiconductor device with contact structure22 Apr 2025US 12,283,518 B2Nanya Technology Corporation
- Lithography processes for dual damascene structures25 Dec 2025US 2025/0390026 A1APPLIED Materials.Inc.
- Semiconductor Device and Method of Forming an Embedded Redistribution Layer2 Oct 2025US 2025/0309172 A1STATS ChipPAC Pte. Ltd.
- Ic die fabrication with self-alignment of multi-level features18 Sep 2025US 2025/0293149 A1Intel Corporation
- Selective recessing to form a fully aligned via1 May 2025US 2025/0140611 A1Adeia Semiconductor Solutions LLC
- Method for fabricating photomask and method for fabricating semiconductor device with damascene structure27 Feb 2025US 2025/0069946 A1Nanya Technology Corporation
Most cited
By later US patents
- Damascene wiring with flat surface86US 6,028,362 AYamaha Corporation · 2000
- Method for reducing photolithographic steps in a semiconductor interconnect process85US 5,741,624 AMicron Technology, Inc. · 1998
- Hard mask method for transferring a multi-level photoresist pattern81US 5,821,169 ASharp Kabushiki Kaisha · 1998
- Damascene structure fabricated using a layer of silicon-based photoresist material75US 6,204,168 B1APPLIED Materials.Inc. · 2001
- Dual damascene process using single photoresist process48US 5,877,075 AIndustrial Technology Research Institute · 1999