Method for reducing photolithographic steps in a semiconductor interconnect process
AssigneeMicron Technology, Inc.
InventorsNanseng Jeng, Christophe Pierrat
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AssigneeMicron Technology, Inc.
InventorsNanseng Jeng, Christophe Pierrat
Estimating the term…
A semiconductor wafer having a first layer and overlying insulating layer receives a photoresist layer. A first photoresist area is exposed to light having a first dosage, while a second, adjacent photoresist area is concurrently exposed to light having a second dosage. The first area and second area then are concurrently developed to partially expose the photoresist layer. The partial exposure removes photoresist within the first area to one depth and within the second area to a second depth. The second depth differs from the first depth. In one embodiment the second depth extends through the photoresist down to the insulating layer. After subsequently performing a contact and/or trench etch through the exposed insulating layer and removing excess photoresist above the insulating layer, conductive material is deposited in the contact/trench opening and over the insulating layer. The result is an upper conductive layer coupled to the first layer via a contact or other conductive connection.
A method for partially developing a layer of photoresist on a semiconductor wafer, comprising the steps of:
A method for connecting a first layer and a second layer of a semiconductor wafer, the second layer being above the first layer for at least a portion of the first layer and at least a portion of the second layer, the second layer comprising a conductive material, the method comprising the steps of:
A method for forming a contact and upper conductive layer coupled to a first layer of a semiconductor wafer, the upper conductive layer being above the first layer for at least a portion of the first layer and at least a portion of the upper conductive layer, the method comprising the steps of:
Dependencies are inferred from the claim text.