US 5,877,075 AGranted

Dual damascene process using single photoresist process

AssigneeIndustrial Technology Research Institute

InventorsChang-Ming Dai, Jammy Chin-Ming Huang

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Abstract

A simplified method is disclosed for forming dual damascene patterns using a single photoresist process. A substrate is provided with a tri-layer of insulation formed thereon. A layer of photoresist is formed on the substrate and is imaged with a hole pattern by exposure through a dark field mask. Hole is formed in the photoresist by a wet etch. As a key step, the photoresist is next subjected to post-exposure bake such that the sensitivity of the photoresist is still retained. The same photoresist layer is then exposed for the second time for aligned line patterning using a "clear-field" mask. The line patterned region is cross-linked by performing pre-silylation bake, which region in turn is not affected by the subsequent silylation process that forms a silicon rich mask in the field surrounding the hole and line patterns. The vertical hole is transferred into the middle layer of the underlying composite layer by dry etching. Twine pattern which is next formed in the same photoresist layer is transferred into the top layer of the composite layer while at the same time the hole pattern is transferred to the bottom layer. Having thus formed the vertical hole interconnect and line trench into the insulation layer, metal is deposited into the dual damascene pattern. Any excess metal on the surface of the insulating layer is then removed by any number of ways including chemical-mechanical polishing, thereby planarizing the surface and readying it for the next semiconductor process.

A method of forming a dual damascene pattern employing a single photoresist layer comprising the steps of:

providing a substrate having a composite layer of insulation deposited thereon whereby said composite layer comprises a first layer of dielectric separated from a second layer of dielectric by an intervening intermediate layer of dielectric;
forming a layer of photoresist on said composite layer of dielectric insulation;
hole patterning said layer of photoresist by exposing said photoresist using a dark field photo mask;
post-exposure baking of said layer of photoresist;
performing a wet development of said layer of photoresist;
line patterning said layer of photoresist by exposing said photoresist using a clear field photo mask;
performing a pre-silylation bake of said layer of photoresist;
treating a surface portion of said layer of photoresist with a silylation process thereby forming a silylated layer of silylation regions in said layer of photoresist;
etching said second layer of dielectric underlying said layer of photoresist using said silylated layer of said layer of photoresist as a mask thereby transferring said hole pattern in said layer of photoresist into said second layer of dielectric;
etching said intermediate layer of dielectric underlying said second layer of dielectric using said silylated layer of said layer of photoresist as a mask thereby transferring said hole pattern in said layer of photoresist into said intermediate layer of dielectric;
etching said layer of photoresist to form said line pattern adjacent to said silylated layer in said layer of photoresist;
etching said composite layer of insulation thereby transferring said line pattern in said layer of photoresist into said second layer of dielectric to form a line trench, and simultaneously transferring said hole pattern in said intermediate layer of dielectric into said first layer of dielectric to form a contact hole;
removing said layer of photoresist;
and
depositing metal into said trench and said hole to form a dual damascene structure.

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Abstract

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