Method for fabricating a semiconductor device with a composite barrier structure

A method for fabricating a semiconductor device, comprising:

• forming a first etch stop layer on a top surface of a substrate;
• forming a first dielectric layer on a top surface of the first etch stop layer;
• forming a first hard mask layer on a top surface of the first dielectric layer;
• forming a first mask layer on a top surface of the first hard mask layer;
• via the first mask layer, patterning the first hard mask layer to form a first hard mask opening so as to expose a portion of the top surface of the first dielectric layer, wherein a pattern of the first mask layer matches a width of the first hard mask opening;
• via an ashing process, removing the first mask layer on the first hard mask layer after the first hard mask opening is formed to expose the top surface of the first hard mask layer;
• after removing the first mask layer, forming a feature opening, via an etching process for etching the first dielectric layer, to expose the top surface of the substrate to remove a portion of the first dielectric layer and by removing a portion of the first etch stop layer, such that a width of the feature opening through the first dielectric layer is equal to a width of the feature opening through the first etch stop layer, wherein the width of the feature opening is equal to a width of the first hard mask opening, wherein a bottom wall of the feature opening is formed on the top surface of the substrate, wherein etching residues are left on inner surfaces of the feature opening and the top surface of the substrate after the ashing process to remove the first mask layer and the etching process to etch the first dielectric layer;
• performing a pre-cleaning treatment comprising a pre-cleaning solution to the first hard mask opening and the feature opening for cleaning the etching residues therein at the same time, wherein the pre-cleaning treatment comprises:
• applying the pre-cleaning solution into the first hard mask opening and the feature opening for a predetermined time;
• rinsing the first hard mask opening and the feature opening by deionized water to remove the pre-cleaning solution;
• performing a cleaning process to the first hard mask opening and the feature opening;
• conformally forming a barrier layer in the first hard mask opening and the feature opening, wherein a bottom surface of the barrier layer is in contact with the top surface of the substrate, such that a height of the barrier layer is equal to a sum of a thickness of the first etch stop layer and a thickness of the first dielectric layer;
• conformally forming an assisting blocking layer on the barrier layer;
• and
• forming a conductive feature on the assisting blocking layer, wherein a top surface of the barrier layer, a top surface of the assisting blocking layer, a top surface of the conductive feature are coplanar with a top surface of the first dielectric layer;
• wherein the pre-cleaning solution comprises a chelating agent and a corrosion inhibitor to reduce a metal corrosion during the cleaning process;
• wherein the barrier layer comprises tantalum;
• wherein the assisting blocking layer comprises copper manganese alloy.