Selective recessing to form a fully aligned via

An interconnect structure for a semiconductor device, the interconnect structure comprising:

• a first dielectric layer;
• a first metal line, a second metal line, and a third metal line, the first metal line, the second metal line, and the third metal line extending parallel to each other in a first direction and formed in a first metallization layer, wherein the second metal line is disposed adjacent to and between the first metal line and the third metal line;
• a first region comprising (i) a first segment of the first metal line and (ii) a first segment of the second metal line, wherein the first segment of the first metal line and the first segment of the second metal line are recessed relative to a top surface of the first dielectric layer;
• and
• a second region comprising a first segment of the third metal line, the first segment of the third metal line comprising a top surface at substantially the same level as the top surface of the first dielectric layer.