Ic die fabrication with self-alignment of multi-level features

An apparatus comprising:

• an integrated circuit (IC) interconnect line, wherein the line comprises a first line segment that intersects a second, non-parallel line segment;
• a first IC interconnect via over or below the IC interconnect line, wherein the first IC interconnect via is in direct contact with the first segment of IC interconnect line, and wherein the via comprises sidewalls within a first dimension of the IC that have no misalignment with sidewalls of the first segment;
• and
• a second IC interconnect via over or below the IC interconnect line, wherein the second IC interconnect via is in direct contact with the second segment of IC interconnect line, and wherein the via comprises sidewalls within a second dimension of the IC that have no misalignment with sidewalls of the second segment.

A method comprising:

• receiving an integrated circuit (IC) workpiece comprising a thin film;
• applying a resist over the thin film;
• exposing at least two regions of the resist with different non-zero doses imaged through a single mask;
• developing a first resist feature associated with a first of the non-zero doses;
• transferring the first resist feature into an underlying film of the IC workpiece;
• developing a second resist feature associated with a second of the non-zero exposure doses;
• and
• transferring the second resist feature into the thin film.