G01R 31/3183
Generation of test inputs
Official title: Generation of test inputs, e.g. test vectors, patterns or sequences
G01R31/3183 (Generation of test inputs) appears on 2,020 US grants and 1,550 published applications in this corpus.
Search patents in G01R- Granted patents
- 2,020
- Published applications
- 1,550
- Assignees
- 543
- Inventors
- 3,885
- Latest grant
- 29 Sep 2026
Filings by year
| Year | Granted patents | Published applications |
|---|---|---|
| 1976 | 3 | 0 |
| 1977 | 1 | 0 |
| 1978 | 1 | 0 |
| 1979 | 2 | 0 |
| 1980 | 2 | 0 |
| 1981 | 0 | 0 |
| 1982 | 2 | 0 |
| 1983 | 2 | 0 |
| 1984 | 2 | 0 |
| 1985 | 1 | 0 |
| 1986 | 5 | 0 |
| 1987 | 16 | 0 |
| 1988 | 11 | 0 |
| 1989 | 11 | 0 |
| 1990 | 10 | 0 |
| 1991 | 10 | 0 |
| 1992 | 8 | 0 |
| 1993 | 8 | 0 |
| 1994 | 26 | 0 |
| 1995 | 46 | 0 |
| 1996 | 53 | 0 |
| 1997 | 41 | 0 |
| 1998 | 39 | 0 |
| 1999 | 49 | 0 |
| 2000 | 49 | 0 |
| 2001 | 58 | 12 |
| 2002 | 55 | 73 |
| 2003 | 66 | 92 |
| 2004 | 83 | 102 |
| 2005 | 71 | 90 |
| 2006 | 99 | 92 |
| 2007 | 91 | 94 |
| 2008 | 83 | 102 |
| 2009 | 75 | 87 |
| 2010 | 69 | 56 |
| 2011 | 84 | 36 |
| 2012 | 63 | 44 |
| 2013 | 50 | 39 |
| 2014 | 46 | 32 |
| 2015 | 37 | 46 |
| 2016 | 48 | 47 |
| 2017 | 46 | 34 |
| 2018 | 42 | 46 |
| 2019 | 65 | 60 |
| 2020 | 63 | 61 |
| 2021 | 57 | 59 |
| 2022 | 73 | 74 |
| 2023 | 70 | 56 |
| 2024 | 64 | 52 |
| 2025 | 38 | 29 |
| 2026 | 26 | 35 |
By publication year. Applications have been published since 2001. 2026 runs to 8 Oct.
Subgroups
Granted patents
- G01R 31/318342By preliminary fault modelling821
- G01R 31/318307Computer-aided328
- G01R 31/318371Methodologies therefor239
- G01R 31/318385Random or pseudo-random test pattern229
- G01R 31/318314Tools228
- G01R 31/318364As a result of hardware simulation183
- G01R 31/318335Test pattern compression or decompression149
- G01R 31/318328For delay tests107
Recent patents
- Testing apparatus for high-rate transmission and reception of signals between device under test and semiconductor testing apparatus29 Sep 2026US 12,748,144 B2Advantest Corporation
- Seamless universal verification methodology1 Sep 2026US 12,724,070 B1Amazon Technologies, Inc.
- Electronic circuit simulation based on random telegraph signal noise25 Aug 2026US 12,716,932 B2Taiwan Semiconductor Manufacturing Company.Ltd
- Method and system of developing and executing test program for verifying DUT18 Aug 2026US 12,710,468 B2Microtest S.p.A.
- Automated test equipment and method using a trigger generation11 Aug 2026US 12,704,547 B2Advantest Corporation
- Jtag-based soc design verification on emulation1 Oct 2026US 2026/0299020 A1Microsoft Technology Licensing, LLC
- Methods, systems, and computer readable media for providing a test system with emulation modeling1 Oct 2026US 2026/0299022 A1Keysight Technologies, Inc.
- Testing large-scale electronic systems constituted of many functional blocks1 Oct 2026US 2026/0299023 A1Krivya Semicon Private Limited
- Test apparatus and method for operating a test apparatus17 Sep 2026US 2026/0276706 A1Advantest Corporation
- Clockless pulse detection circuit27 Aug 2026US 2026/0251711 A1STMicroelectronics International N. V.
Most cited
By later US patents
- Method and system for creating and validating low level description of electronic design from higher level, behavior-oriented description, including interactive system for hierarchical display of control and dataflow information324US 5,801,958 ALSI Logic Corporation · 1998
- Methods and apparatus for system fault diagnosis and control310US 4,649,515 AWestinghouse Electric Corp. · 1987
- Cell architecture to reduce customization in a semiconductor device278US 6,580,289 B2ViASIC, Inc. · 2003
- Method and system for creating, deriving and validating structural description of electronic system from higher level, behavior-oriented description, including interactive schematic design and simulation252US 5,544,067 ALSI Logic Corporation · 1996
- Method of generating instruction sequences for controlling data flow processes231US 5,136,705 ATektronix, Inc. · 1992