G01R 31/318385
Random or pseudo-random test pattern
Official title: {Random or pseudo-random test pattern}
G01R31/318385 (Random or pseudo-random test pattern) appears on 229 US grants and 145 published applications in this corpus.
Search patents in G01R- Granted patents
- 229
- Published applications
- 145
- Assignees
- 108
- Inventors
- 453
- Latest grant
- 26 May 2026
Filings by year
| Year | Granted patents | Published applications |
|---|---|---|
| 1976 | 1 | 0 |
| 1977 | 0 | 0 |
| 1978 | 0 | 0 |
| 1979 | 1 | 0 |
| 1980 | 1 | 0 |
| 1981 | 0 | 0 |
| 1982 | 1 | 0 |
| 1983 | 0 | 0 |
| 1984 | 1 | 0 |
| 1985 | 0 | 0 |
| 1986 | 2 | 0 |
| 1987 | 4 | 0 |
| 1988 | 3 | 0 |
| 1989 | 6 | 0 |
| 1990 | 3 | 0 |
| 1991 | 1 | 0 |
| 1992 | 3 | 0 |
| 1993 | 1 | 0 |
| 1994 | 8 | 0 |
| 1995 | 10 | 0 |
| 1996 | 5 | 0 |
| 1997 | 8 | 0 |
| 1998 | 2 | 0 |
| 1999 | 6 | 0 |
| 2000 | 5 | 0 |
| 2001 | 4 | 1 |
| 2002 | 6 | 9 |
| 2003 | 6 | 8 |
| 2004 | 13 | 11 |
| 2005 | 10 | 13 |
| 2006 | 6 | 5 |
| 2007 | 12 | 5 |
| 2008 | 2 | 4 |
| 2009 | 6 | 12 |
| 2010 | 9 | 6 |
| 2011 | 3 | 6 |
| 2012 | 7 | 7 |
| 2013 | 6 | 3 |
| 2014 | 5 | 2 |
| 2015 | 3 | 5 |
| 2016 | 1 | 3 |
| 2017 | 7 | 2 |
| 2018 | 3 | 5 |
| 2019 | 6 | 7 |
| 2020 | 7 | 4 |
| 2021 | 7 | 9 |
| 2022 | 8 | 9 |
| 2023 | 9 | 3 |
| 2024 | 7 | 4 |
| 2025 | 3 | 1 |
| 2026 | 1 | 1 |
By publication year. Applications have been published since 2001. 2026 runs to 8 Oct.
Recent patents
- Semiconductor integrated circuit device and evaluation system26 May 2026US 12,638,502 B2Rohm Co., Ltd.
- Detecting hardware errors23 Sep 2025US 12,422,480 B1Amazon Technologies, Inc.
- Forward error correction (FEC) encoded physical layer test pattern24 Jun 2025US 12,339,320 B2Cisco Technology, Inc.
- Compression-based scan test system1 Apr 2025US 12,265,121 B2STMicroelectronics International N. V.
- Random number generation testing systems and methods5 Nov 2024US 12,135,352 B2Advantest Corporation
- Circuit And Method For Performing Functional Safety Test, Neural Processing Unit, And Storage Medium5 Mar 2026US 2026/0064926 A1Beijing Horizon Information Technology Co., Ltd.
- Secure built-in self-test (bist)2 Oct 2025US 2025/0306101 A1Intel Corporation
- Compression-based scan test system28 Nov 2024US 2024/0393393 A1STMicroelectronics International N. V.
- Semiconductor integrated circuit device and evaluation system26 Sep 2024US 2024/0319271 A1Rohm Co., Ltd.
- Techniques for infield testing of cryptographic circuitry8 Aug 2024US 2024/0264231 A1Intel Corporation
Most cited
By later US patents
- Arithmetic built-in self test of multiple scan-based integrated circuits174US 5,991,898 AMentor Graphics Corporation · 1999
- Parallel decompressor and related methods and apparatuses152US 5,991,909 AMentor Graphics Corporation · 1999
- Method of partitioning, testing and diagnosing a VLSI multichip package and associated structure119US 4,817,093 AInternational Business Machines Corporation · 1989
- Dynamic process for the generation of biased pseudo-random test patterns for the functional verification of hardware designs119US 5,202,889 AInternational Business Machines Corporation · 1993
- Weighted random pattern testing apparatus and method118US 4,801,870 AInternational Business Machines Corporation · 1989