Compression-based scan test system

A system comprising:

• a test system configured to be coupled to a circuit under test (CUT), the test system comprising:
• a pattern generation circuit comprising a Pseudo-Random Pattern Generator (PRPG) coupled to a first clock input;
• a plurality of scan chains coupled to an output of the PRPG and configured to be coupled to the CUT, the plurality of scan chains comprising registers having clock inputs coupled to a second clock input;
• an evaluation circuit coupled to the plurality of scan chains, the evaluation circuit configured to capture response patterns generated by the CUT in the plurality of scan chains;
• and
• a control circuit configured to modify a bit distribution of test patterns generated by the PRPG with respect to the plurality of scan chains by:
• freezing at least one clock cycle of a first clock signal while a second clock signal is active, wherein freezing the at least one clock cycle of the first clock signal is configured to cause a same pattern output by the PRPG to be clocked into the plurality of scan chains, or
• freezing at least one clock cycle of the second clock signal while the first clock signal is active, wherein freezing the at least one clock cycle of the second clock signal prevents a first pattern output by the PRPG from being clocked into the plurality of scan chains.

An integrated circuit comprising:

• a control circuit configured to produce a modified clock signal based on an input clock signal, and freeze at least one clock cycle of the modified clock signal while the input clock signal is active;
• a Pseudo-Random Pattern Generator (PRPG) based decompressor having an input configured to receive at least one seed value, wherein the PRPG-based decompressor comprises a clock input configured to receive the input clock signal;
• a plurality of scan chains coupled to the PRPG-based decompressor, the plurality of scan chains having registers with clock inputs configured to receive the modified clock signal, wherein the modified clock signal is configured to prevent a first pattern output by the PRPG from being clocked into the plurality of scan chains when the at least one clock cycle of the modified clock signal is frozen;
• a compressor coupled to the plurality of scan chains, the compressor comprising a clock input configured to receive the input clock signal;
• and
• a circuit under test (CUT) coupled to the plurality of scan chains.