Parallel decompressor and related methods and apparatuses

An apparatus comprising a dual mode pseudo-random pattern generator (PRPG)/parallel decompressor to generate pseudo-random data vectors using a single LFSR while operating in a first mode, and to generate deterministic partially specified data vectors while operating in a second mode, with multiple portions of each deterministic partially specified data vector being generated in parallel using the same single LFSR.

An integrated circuit having built-in self-test (BIST) circuitry including a parallel data generator formed with a linear feedback shift register (LFSR) and multiple pluralities of serially coupled flip-flops, wherein the LFSR to concurrently output in parallel different data bits to different ones of the multiple pluralities of serially coupled flip-flops, and the multiple pluralities of serially coupled flip-flops concurrently feed back in parallel different data bits to different parts of the LFSR.

An integrated circuit having built-in self-test (BIST) circuitry including a multi-mode pseudo-random pattern generator (PRPG)/parallel decompressor to generate pseudo-random data vectors using a single LFSR while operating in a first mode, and to generate deterministic partially specified data vectors while operating in a second mode, with multiple portions of each of the deterministic partially specified data vectors being generated in parallel using the same single LFSR used to generate the pseudo-random data vectors of the first mode.

An apparatus comprising a first and a second integrated circuit having a corresponding first and a second parallel data generator with the first parallel data generator providing either an output data bit from a linear feedback shift register (LFSR) of the first parallel data generator, or a copy of a feedback data bit to the LFSR of the first parallel data generator, as input to a LFSR of the second parallel data generator.

An apparatus comprising a first and a second integrated circuit correspondingly having a first and a second dual purpose pseudo-random pattern generator (PRPG)/parallel decompressor with the first PRPG/parallel decompressor providing either an output data bit from a linear feedback shift register (LFSR) of the first PRPG/parallel decompressor, or a copy of a feedback data bit to the LFSR of the first PRPG/parallel decompressor, as input to a LFSR of the second PRPG/parallel decompressor.

A method for loading a variable length data vector into a parallel decompressor comprising:

• a) resetting a linear feedback shift register (LFSR);
• and
• b) shifting a variable length data seed into the LFSR and then serially to a plurality of serially coupled flip-flop chains, overriding selected ones of data bits output from one flip-flop chain to another flip-flop chain.

A storage medium having stored therein a first plurality of programming instructions to be executed by a computer system to insert built-in self-test (BIST) circuitry into an integrated circuit design, the BIST circuitry having a parallel decompressor to concurrently generate in parallel multiple portions of deterministic partially specified data vectors, wherein the parallel decompressor is formed with a LFSR and multiple flip-flop chains with the LFSR and the multiple flip-flop chains being structurally coupled to each other in a manner that allows a plurality of different data bits to be concurrently provided in parallel to different ones of the flip-flop chains and a plurality of different data bits to be concurrently feed back to different parts of the LFSR.

A computer system comprising:

• a storage medium having stored therein a first plurality of programming instructions;
• and
• an execution unit, coupled to the storage medium, to execute programming instructions stored in the storage medium including said first plurality of programming instructions which, when executed by said execution unit, insert a built-in self-test (BIST) circuitry into an integrated circuit design, the BIST circuitry having a parallel decompressor to concurrently generate in parallel multiple portions of deterministic partially specified data vectors from compressed data seeds, wherein the parallel decompressor being formed with a single LFSR and multiple flip-flop chains, with the LFSR and the multiple flip-flop chains being structurally coupled to each other in a manner that allows a plurality of different data bits to be concurrently provided in parallel to different ones of the flip-flop chains and a plurality of different data bits to be concurrently feed back to different parts of the LFSR.

A storage medium having stored therein an integrated circuit design including built-in self-test (BIST) circuitry having a parallel decompressor to concurrently generate in parallel multiple portions of a deterministic data vector, the parallel decompressor being formed with a single LFSR and multiple flip-flop chains with the LFSR and the multiple flip-flop chains being structurally coupled to each other in a manner that allows a plurality of different data bits to be concurrently provided in parallel to different ones of the flip-flop chains, and a plurality of different data bits to be concurrently feed back to different parts of the LFSR.