Forward error correction (FEC) encoded physical layer test pattern
AssigneeCisco Technology, Inc.
InventorsFabio Bottoni, Alessandro Cavaciuti
Life of this patent
Estimating the term…
Abstract
Techniques are provided for generating a physical test pattern that is framed within an Forward Error Correction (FEC)-encoded stream or sequence. Accordingly, in one embodiment, a method is provided that includes obtaining a physical layer test pattern for testing operation of a device; generating an FEC framed test pattern that embeds the physical layer test pattern into an FEC-encoded stream; and applying the FEC framed test pattern to the transceiver device to test physical layer operation of the device and to obtain FEC error statistics.
Claims20
A method comprising:
- obtaining a physical layer test pattern for testing operation of a device;
- generating a forward error correction (FEC) framed test pattern by deriving from the physical layer test pattern a plurality of test pattern payloads, translating the plurality of test pattern payloads to a plurality of inverse encoded test pattern payloads that, when FEC encoded, produce the plurality of test pattern payloads, and forming the FEC framed test pattern with a sequence of codewords each of which includes a respective one of the plurality of inverse encoded test pattern payloads;
- and
- applying the FEC framed test pattern to the device to test physical layer operation of the device and to obtain FEC error statistics and information indicating operational performance of the device as a result of stress caused by the physical layer test pattern.
An apparatus comprising:
- a memory;
- an input/output interface configured to enable connectivity with a device to be tested;
- and
- at least one processor coupled to the memory and the input/output interface, wherein the at least one processor is configured to perform operations including:
- generating a forward error correction (FEC) framed test pattern by deriving from a physical layer test pattern a plurality of test pattern payloads, translating the plurality of test pattern payloads to a plurality of inverse encoded test pattern payloads that, when FEC encoded, produce the plurality of test pattern payloads, and forming the FEC framed test pattern with a sequence of codewords each of which includes a respective one of the plurality of inverse encoded test pattern payloads;
- and
- applying the FEC framed test pattern to the device to test physical layer operation of the device and to generate FEC error statistics and information indicating operational performance of the device as a result of stress caused by the physical layer test pattern.
A system comprising:
- a device having one or more physical layer functions;
- and
- a testing equipment configured to connect to the device, wherein the testing equipment is configured to:
- generate a forward error correction (FEC) framed test pattern by deriving from a physical layer test pattern a plurality of test pattern payloads, translating the plurality of test pattern payloads to a plurality of inverse encoded test pattern payloads that, when FEC encoded, produce the plurality of test pattern payloads, and forming the FEC framed test pattern with a sequence of codewords each of which includes a respective one of the plurality of inverse encoded test pattern payloads;
- and
- apply the FEC framed test pattern to the device to test physical layer operation of the device and to generate FEC error statistics and information indicating operational performance of the device as a result of stress caused by the physical layer test pattern.
Dependencies are inferred from the claim text.