Weighted random pattern testing apparatus and method
AssigneeInternational Business Machines Corporation
InventorsEdward B. Eichelberger, Eric Lindbloom, Franco Motika, John A. Waicukauski
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AssigneeInternational Business Machines Corporation
InventorsEdward B. Eichelberger, Eric Lindbloom, Franco Motika, John A. Waicukauski
Estimating the term…
A method and apparatus for testing very large scale integrated circuit devices, most particularly Level Sensitive Scan Design (LSSD) devices, by applying differently configured sequences of pseudo-random patterns in parallel to each of the input terminals of the device under test, collecting the output responses from each of the output terminals in parallel, combining these outputs to obtain a signature which is a predetermined function of all of the sequences of parallel outputs and comparing the test signature with a known good signature obtained by computer simulation. The input test stimuli are further altered in a predetermined fashion as a function of the structure of the device to be tested, to individually weight the inputs in favor of more of less binary ones or zeros.
A method for production testing of complex integrated circuit devices and producing data for diagnosing faults in those devices failing the production test, comprising the steps of;
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