Method of partitioning, testing and diagnosing a VLSI multichip package and associated structure

A method for partitioning and testing a multi-chip packaging structure having at least a packaging substrate, a plurality of chips mounted on said substrate, and test circuitry incorporated into said package comprising the steps of:

• electronically inhibiting all chips on said packaging structure from being active, except for a particular chip partition under test;
• generating a set of tailored reproducible random patterns from an initial pattern for the partition under test;
• selecting a predetermined number of random patterns to be applied to the partition under test;
• applying said tailored reproducible set of random patterns to the partition under test;
• counting the number of random patterns being applied to the partition under test so that when said predetermined number of random patterns is reached no more patterns are applied;
• generating an actual partition under test compressed signature from said output patterns;
• storing said actual partition under test compressed signature;
• retrieving a simulated compressed signature of the partition under test and
• comparing said simulated compressed signature and said actual partition under test compressed signature.

In a multi-chip packaging structure having at least a packaging substrate having chip sites on the top surface thereof, and a plurality of chips mounted on said substrate, integral test circuitry means comprising:

• means for electronically inhibiting all chips on said packaging structure from being active, except for the particular unit under test;
• means for generating and applying a set of tailored reproducible random patterns, from an initial pattern, to the inputs of the unit under test;
• means for creating an actual compressed signature of sid unit under test in response to said set of tailored reproducible random patterns;
• and;
• means for comparing said actual compressed signature of said unit under test with a signature obtained by simulation means.