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US 12,638,502 B2Granted
Semiconductor integrated circuit device and evaluation system
AssigneeRohm Co., Ltd.
InventorsHideki Miyoshi, Akira Uryu
Life of this patent
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Abstract
Provided is a semiconductor integrated circuit device including a pseudo-random pattern generator configured to output a pseudo-random pattern, a terminal for externally outputting an output of the pseudo-random pattern generator or an evaluation result of noise tolerance evaluated on the basis of the pseudo-random pattern.
Claims8
A semiconductor integrated circuit device comprising:
- a pseudo-random pattern generator configured to output an output of the pseudo-random pattern generator;
- and
- a terminal configured to externally output an evaluation result of noise tolerance, wherein
- the evaluation result of noise tolerance is evaluated on a basis of the output of the pseudo-random pattern generator, and
- the output of the pseudo-random pattern generator is synchronized during a first period and has a random feature during a second period shorter than the first period.
2 more elements
Dependencies are inferred from the claim text.