Seamless universal verification methodology

A computer-implemented method comprising:

• compiling a utility module to provide a model and a testbench environment within a Universal Verification Methodology (UVM) system, the model and the testbench environment represented by different classes of a first class script and the utility module based in part on input from a template code and input from a configuration object, the configuration object comprising an address map code and the testbench environment comprising agents to test an integrated circuit using the UVM system;
• determining a change in the configuration object;
• automatically generating a second class script using the utility module and based in part on the change in the configuration object, wherein specifications in the template code and associated with the UVM system remain unchanged for the second class script;
• and
• providing the second class script for execution to test the integrated circuit.

A non-transitory computer-storage medium storing instructions configured to instruct at least one processor to:

• compile a utility module to provide a model and a testbench environment within a Universal Verification Methodology (UVM) system, the model and the testbench environment represented by different classes of a first class script and the utility module based in part on input from a template code and input from a configuration object, the configuration object comprising an address map code and the testbench environment comprising agents to test an integrated circuit using the UVM system;
• determine a change in the configuration object;
• automatically generate a second class script using the utility module and based in part on the change in the configuration object, wherein specifications in the template code and associated with the UVM system remain unchanged for the second class script;
• and
• execute the second class script within the UVM environment to test the integrated circuit.