G01R 31/318371
Methodologies therefor
Official title: {Methodologies therefor, e.g. algorithms, procedures}
G01R31/318371 (Methodologies therefor) appears on 239 US grants and 168 published applications in this corpus.
Search patents in G01R- Granted patents
- 239
- Published applications
- 168
- Assignees
- 124
- Inventors
- 537
- Latest grant
- 8 Jul 2025
Filings by year
| Year | Granted patents | Published applications |
|---|---|---|
| 1976 | 1 | 0 |
| 1977 | 1 | 0 |
| 1978 | 0 | 0 |
| 1979 | 1 | 0 |
| 1980 | 1 | 0 |
| 1981 | 0 | 0 |
| 1982 | 0 | 0 |
| 1983 | 0 | 0 |
| 1984 | 1 | 0 |
| 1985 | 1 | 0 |
| 1986 | 2 | 0 |
| 1987 | 6 | 0 |
| 1988 | 0 | 0 |
| 1989 | 3 | 0 |
| 1990 | 0 | 0 |
| 1991 | 4 | 0 |
| 1992 | 0 | 0 |
| 1993 | 1 | 0 |
| 1994 | 3 | 0 |
| 1995 | 5 | 0 |
| 1996 | 14 | 0 |
| 1997 | 7 | 0 |
| 1998 | 2 | 0 |
| 1999 | 5 | 0 |
| 2000 | 6 | 0 |
| 2001 | 11 | 1 |
| 2002 | 8 | 12 |
| 2003 | 7 | 4 |
| 2004 | 8 | 6 |
| 2005 | 6 | 15 |
| 2006 | 8 | 14 |
| 2007 | 10 | 8 |
| 2008 | 9 | 5 |
| 2009 | 9 | 8 |
| 2010 | 6 | 4 |
| 2011 | 7 | 2 |
| 2012 | 6 | 8 |
| 2013 | 3 | 2 |
| 2014 | 3 | 6 |
| 2015 | 4 | 10 |
| 2016 | 14 | 6 |
| 2017 | 5 | 8 |
| 2018 | 5 | 8 |
| 2019 | 11 | 4 |
| 2020 | 7 | 8 |
| 2021 | 6 | 4 |
| 2022 | 10 | 8 |
| 2023 | 7 | 3 |
| 2024 | 2 | 6 |
| 2025 | 3 | 2 |
| 2026 | 0 | 6 |
By publication year. Applications have been published since 2001. 2026 runs to 8 Oct.
Recent patents
- Random instruction-side stressing in post-silicon validation8 Jul 2025US 12,353,307 B2Synopsys, Inc.
- Forward error correction (FEC) encoded physical layer test pattern24 Jun 2025US 12,339,320 B2Cisco Technology, Inc.
- Testing system and testing method15 Apr 2025US 12,276,698 B2ASMedia Technology Inc.
- Method and apparatus for integrated circuit testing11 Jun 2024US 12,007,439 B1Winbond Electronics Corp.
- Electronic device test method and test device28 May 2024US 11,994,558 B2Realtek Semiconductor Corp.
- Testing method for electronic device and test system18 Jun 2026US 2026/0169068 A1Samsung Electronics Co., Ltd.
- Integrated circuit design using neural networks7 May 2026US 2026/0127347 A1NVIDIA Corporation
- Method of using a test pattern for testing functionalities of external devices when an item is attached to a vehicle2 Apr 2026US 2026/0092970 A1Volvo Car Corporation
- Test apparatus, test method, and program26 Mar 2026US 2026/0086148 A1Advantest Corporation
- Closed loop adaptive generative adversarily network filter26 Mar 2026US 2026/0086149 A1Tektronix, Inc.
Most cited
By later US patents
- Methods and apparatus for system fault diagnosis and control310US 4,649,515 AWestinghouse Electric Corp. · 1987
- Test pattern compression for an integrated circuit test environment128US 6,327,687 B12001
- Optimal test generation for finite state machine models89US 4,991,176 AAT&T Bell Laboratories · 1991
- Test pattern compression for an integrated circuit test environment86US 6,543,020 B22003
- Method for verification of combinational circuits using a filtering oriented approach84US 6,086,626 AFijutsu Limited · 2000