Test pattern compression for an integrated circuit test environment

A method that computes a compressed test pattern used to load scan cells within an integrated circuit to test for faults, comprising:

• providing a decompressor having one or more input injectors;
• assigning input variables to bits applied serially to the one or more input injectors;
• and
• generating a compressed test pattern by using symbolic expressions associated with the scan cells, wherein the symbolic expressions include linear combinations of the input variables that are applied concurrently to the decompressor as the decompressor decompresses the input variables.

An apparatus that computes a compressed test pattern to test an integrated circuit, comprising:

• means for generating symbolic expressions that are associated with scan cells within the integrated circuit, the symbolic expressions associated with loading a decompressor with externally applied input variables currently as the decompressor continually decompresses;
• means for generating a test cube having only a portion of the scan cells assigned predetermined values;
• means for formulating a set of equations by equating the assigned values in the scan cells to the symbolic expressions;
• and
• means for solving the equations to obtain the compressed test pattern.

A computer-readable medium on which is stored computer-readable instructions for performing the following:

• providing a decompressor having one or more input injectors;
• assigning input variables to bits applied serially to the one or more input injectors;
• and
• generating a compressed test pattern that use symbolic expressions associated with the scan cells, wherein the symbolic expressions include linear combinations of the input variables applied concurrently to the input injectors as the decompressor continually operates in its normal mode of operation.

A method that computes a compressed test pattern to test an integrated circuit, comprising:

• using simulation, generating symbolic expressions that are associated with simulated scan cells of an integrated circuit, the symbolic expressions being a function of simulated input variables applied concurrently to a simulated decompressor, which is coupled to the scan cells, while the decompressor continually decompresses;
• generating a test cube having only a portion of the scan cells assigned predetermined values;
• formulating a set of equations by equating the assigned values in the scan cells to the symbolic expressions;
• and
• solving the equations to obtain the compressed test pattern.