Electronic device test method and test device
AssigneeRealtek Semiconductor Corp.
InventorsHan-Yun Tsai, Shih-Hung Wang, Ting-Ying Wu
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AssigneeRealtek Semiconductor Corp.
InventorsHan-Yun Tsai, Shih-Hung Wang, Ting-Ying Wu
Estimating the term…
An electronic system test method, comprising: (a) inputting a victim test pattern to a victim signal path of a target electronic system and simultaneously inputting at least one aggressor test pattern to at least one aggressor signal path of the target electronic system, according to a major set of test patterns comprising a plurality of minor set of test patterns; (b) acquiring a output response corresponding to the step (a); and (c) after changing the victim test pattern or the aggressor test pattern, and after repeating the step (a) and the step (b) until all of the major test patterns set are used thereby acquiring a plurality of the output responses, determining a combination level according to the output responses. The victim test pattern is an X bit pattern and the aggressor test pattern is a Y bit pattern, X and Y are positive integers larger than or equal to 3.
An electronic system test method, for estimating the performance of a target electronic system, comprising:
A test device, for estimating the performance of a target electronic system, comprising:
Dependencies are inferred from the claim text.