Random instruction-side stressing in post-silicon validation

A computer-implemented method comprising:

• providing a test template for a multi-threaded hardware system-under-test comprising two execution threads, wherein the test template comprises a branching instruction to a predetermined shared memory address accessible by the two execution threads;
• generating and storing, at said predetermined shared memory address, shared code comprising a sequence of instructions which conform to said test template;
• building, based, at least in part, on said test template, an executable image of a hardware exerciser, wherein the hardware exerciser is adapted to control a test cycle of the hardware system-under-test, and wherein the test cycle comprises generating and executing a test of common use of the shared code by the two execution threads;
• and
• executing said executable image of the hardware exerciser, including the common use of the shared code by the two execution threads.

A computer program product comprising a non-transitory computer-readable storage medium having program instructions embodied therewith, the program instructions executable by at least one hardware processor to:

• provide a test template for a multi-threaded hardware system-under-test comprising two execution threads, wherein the test template comprises a branching instruction to a predetermined shared memory address accessible by the two execution threads;
• generate and store, at said predetermined shared memory address, shared code comprising a sequence of instructions which conform to said test template;
• build, based, at least in part, on said test template, an executable image of a hardware exerciser, wherein the hardware exerciser is adapted to control a test cycle of the hardware system-under-test, and wherein the test cycle comprises generating and executing a test of common use of the shared code by the two execution threads;
• and
• executing said executable image of the hardware exerciser, including the common use of the shared code by the two execution threads .