Method and apparatus for integrated circuit testing

A testing apparatus for an integrated circuit, comprising:

• connecting apparatus, connected to a tester for testing the integrated circuit;
• a storage apparatus, configured to store application programs and scramble equations;
• and
• a processor, coupled to the connecting apparatus and the storage apparatus, and configured to load and execute the application programs, to:
• use the tester to perform a qualitative testing on devices in the integrated circuit by following electrical addresses of the devices, and to introduce an original verification pattern in the qualitative testing, such that a verification pattern corresponding to the original verification pattern can be converted from a raw data of a result of the qualitative testing;
• convert the raw data to a test graph presented by physical addresses, by using pre-determined scramble equations;
• and
• identify portions of the verification pattern appeared in the test graph and compare the portions of the verification pattern with corresponding portions of the original verification pattern by pattern recognition, and correct the pre-determined scramble equations according to comparison result.