G01R 31/318335
Test pattern compression or decompression
Official title: {Test pattern compression or decompression (compression or decompression of scan patterns G01R31/318547; compression or decompression hardware G01R31/31921)}
G01R31/318335 (Test pattern compression or decompression) appears on 149 US grants and 122 published applications in this corpus.
Search patents in G01R- Granted patents
- 149
- Published applications
- 122
- Assignees
- 64
- Inventors
- 232
- Latest grant
- 28 Oct 2025
Filings by year
| Year | Granted patents | Published applications |
|---|---|---|
| 1986 | 1 | 0 |
| 1987 | 2 | 0 |
| 1988 | 1 | 0 |
| 1989 | 0 | 0 |
| 1990 | 1 | 0 |
| 1991 | 0 | 0 |
| 1992 | 1 | 0 |
| 1993 | 0 | 0 |
| 1994 | 1 | 0 |
| 1995 | 1 | 0 |
| 1996 | 2 | 0 |
| 1997 | 2 | 0 |
| 1998 | 1 | 0 |
| 1999 | 3 | 0 |
| 2000 | 1 | 0 |
| 2001 | 1 | 0 |
| 2002 | 2 | 4 |
| 2003 | 2 | 5 |
| 2004 | 3 | 7 |
| 2005 | 1 | 5 |
| 2006 | 3 | 7 |
| 2007 | 9 | 5 |
| 2008 | 5 | 9 |
| 2009 | 8 | 6 |
| 2010 | 6 | 5 |
| 2011 | 10 | 6 |
| 2012 | 3 | 4 |
| 2013 | 4 | 1 |
| 2014 | 2 | 3 |
| 2015 | 4 | 8 |
| 2016 | 7 | 7 |
| 2017 | 7 | 3 |
| 2018 | 7 | 3 |
| 2019 | 12 | 7 |
| 2020 | 5 | 5 |
| 2021 | 6 | 5 |
| 2022 | 8 | 4 |
| 2023 | 10 | 5 |
| 2024 | 5 | 6 |
| 2025 | 2 | 0 |
| 2026 | 0 | 2 |
By publication year. Applications have been published since 2001. 2026 runs to 8 Oct.
Recent patents
- Logic BIST circuit and semiconductor device including same28 Oct 2025US 12,455,317 B2Samsung Electronics Co., Ltd.
- Built-in self-test enhancements9 Sep 2025US 12,411,171 B2QUALCOMM Incorporated
- Scan compression through pin data encoding1 Oct 2024US 12,105,145 B2STMicroelectronics International N. V.
- Scan tree construction17 Sep 2024US 12,092,691 B2Tsinghua University
- Embedded PHY (EPHY) IP core for FPGA20 Aug 2024US 12,066,488 B2SanDisk Technologies LLC
- Test apparatus and method for operating a test apparatus17 Sep 2026US 2026/0276706 A1Advantest Corporation
- Logic bist circuit and semiconductor device including same29 Jan 2026US 2026/0029466 A1Samsung Electronics Co., Ltd.
- Logic bist circuit and semiconductor device including same26 Dec 2024US 2024/0426909 A1Samsung Electronics Co., Ltd.
- Clustering clock chain data for test-time reduction21 Nov 2024US 2024/0385241 A1STMicroelectronics International N. V.
- Embedded PHY (EPHY) IP Core for FPGA7 Nov 2024US 2024/0369628 A1SanDisk Technologies LLC
Most cited
By later US patents
- Method and system for creating and validating low level description of electronic design from higher level, behavior-oriented description, including interactive system for hierarchical display of control and dataflow information324US 5,801,958 ALSI Logic Corporation · 1998
- Method and system for creating and validating low level description of electronic design from higher level, behavior-oriented description, including interactive system for hierarchical display of control and dataflow information226US 5,555,201 ALSI Logic Corporation · 1996
- Parallel decompressor and related methods and apparatuses152US 5,991,909 AMentor Graphics Corporation · 1999
- Test pattern compression for an integrated circuit test environment128US 6,327,687 B12001
- Decompressor/PRPG for applying pseudo-random and deterministic test patterns113US 6,684,358 B12004