Decompressor/PRPG for applying pseudo-random and deterministic test patterns

A system for applying test patterns to scan chains in a circuit-under-test comprising:

• means for applying test patterns to the scan chains;
• means for providing a set of compressed deterministic test patterns to the test pattern applying means;
• means for providing an initial value to the test pattern applying means;
• and
• means for configuring the test pattern applying means to generate, in a pseudo-random phase of operation, a set of pseudo-random patterns from the initial value and to generate, in a deterministic phase of operation, a set of decompressed deterministic test patterns from the set of compressed deterministic test patterns.

A circuit comprising:

• a decompressor/PRPG;
• control circuitry coupled to the decompressor/PRPG and operable to cause the decompressor/PRPG to generate, in a pseudo-random phase of operation, a set of pseudo-random patterns and to generate, in a deterministic phase of operation, a set of decompressed deterministic test patterns from a set of provided compressed deterministic patterns;
• circuit logic;
• and
• scan chains coupled to the circuit logic and operable to receive test patterns generated by the decompressor/PRPG and to capture responses to the test patterns generated by the circuit logic,
• wherein the decompressor/PRPG is operable to decompress a compressed deterministic test pattern as the compressed deterministic test pattern is being provided to the decompressor/PRPG.

A circuit comprising:

• means for applying test patterns to the scan chains;
• means for configuring the test pattern applying means to generate, in a pseudo-random phase of operation, a set of pseudo-random patterns and to generate, in a deterministic phase of operation, a set of deterministic test patterns;
• circuit logic;
• and
• scan chains coupled to the circuit logic and operable to receive test patterns generated by the test pattern applying means and to capture responses to the test patterns generated by the circuit logic.

A method for applying test patterns to scan chains in a circuit-under-test, the method comprising the following steps:

• in a pseudo-random phase of operation:
• a step for providing a initial value;
• a step for generating from the initial value a set of pseudo-random test patterns;
• and
• a step for applying the pseudo-random test patterns to the scan chains in the circuit-under-test;
• in a deterministic phase of operation:
• a step for providing a set of compressed deterministic test patterns;
• a step for decompressing a compressed deterministic test pattern into a decompressed deterministic test pattern as the compressed deterministic test pattern is being provided;
• and
• a step for applying the deterministic test patterns to the scan chains in the circuit-under-test.

A method for applying test patterns to scan chains in a circuit-under-test, the method comprising the following steps:

• a step for providing a set of compressed deterministic test patterns;
• in a pseudo-random phase of operation:
• a step for providing an initial value
• a step for generating from the initial value a set of pseudo-random test patterns;
• and
• a step for applying the pseudo-random test patterns to the scan chains in the circuit-under-test;
• in a deterministic phase of operation:
• a step for decompressing a compressed deterministic test pattern into a decompressed deterministic test pattern as the compressed deterministic test pattern is being provided;
• and
• a step for applying the deterministic test patterns to the scan chains in the circuit-under-test.