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US 12,105,145 B2Granted
Scan compression through pin data encoding
AssigneeSTMicroelectronics International N.V.
InventorsSandeep Jain, Shalini Pathak
Life of this patent
Estimating the term…
Abstract
A method for testing a chip comprising receiving N scan-in chains of test data; using the N scan-in chains of test data to perform tests on the chip; receiving a merged expected test-result and masking-instruction signal on X pins of the chip from the off-chip test equipment, X being less than 2*N; decoding the merged expected test-result and masking-instruction signal to extract N decoded output signals, each of the N decoded output signals corresponding to a respective chain of test results.
Claims20
A method for testing a chip, the method comprising:
- specifying a first pin assignment with N input pins and R merged input pins, N and R being integers, N corresponding to a number of input pins for carrying scan-in chain test data, and R corresponding to a number of input pins for carrying a merged expected test result and a masking instruction signal;
- specifying a second pin assignment with N input pins and M output pins, M being an integer and corresponding to a number of output pins for carrying scan-out chain test data;
- generating an N by M codec;
- integrating the N by M codec and inserting scan chains, wherein device registers are stitched into multiple scan chains and coupled between a compression circuit and a decompression circuit;
- decoding output signals from the merged expected test result and the masking instruction signal received from the R merged input pins;
- receiving the scan-in chain test data;
- and
- comparing the decoded output signals comprising an expected test result with a test result chain.
5 more elements
A chip, comprising:
- N inputs pins, N being an integer and corresponding to a number of input pins for carrying scan-in chain test data;
- R merged input pins, R being an integer and corresponding to a number of input pins for carrying a merged expected test result and a masking instruction signal;
- M output pins, M being an integer and corresponding to a number of output pins for carrying scan-out chain test data;
- a plurality of device registers stitched into multiple scan chains based on an integrated N by M codec, the device registers coupled between a compression circuit and a decompression circuit;
- a decoding logic circuit configured to decode output signals from the merged expected test result and the masking instruction signal received from the R merged input pins;
- and
- a comparator circuit configured to receive the scan-in chain test data and compare the output signals from the decoding logic circuit comprising an expected test result with a test result chain.
4 more elements
A system to test a chip, the system comprising:
- an off-chip test equipment;
- and
- the chip coupled to the off-chip test equipment, the chip comprising:
- N inputs pins, N being an integer and corresponding to a number of input pins for carrying scan-in chain test data;
- R merged input pins, R being an integer and corresponding to a number of input pins for carrying a merged expected test result and a masking instruction signal;
- M output pins, M being an integer and corresponding to a number of output pins for carrying scan-out chain test data;
- a plurality of device registers stitched into multiple scan chains based on an integrated N by M codec, the device registers coupled between a compression circuit and a decompression circuit;
- a decoding logic circuit configured to decode output signals from the merged expected test result and the masking instruction signal received from the R merged input pins;
- and
- a comparator circuit configured to receive the scan-in chain test data and compare the output signals from the decoding logic circuit comprising an expected test result with a test result chain.
7 more elements
Dependencies are inferred from the claim text.