Built-in self-test enhancements
AssigneeQUALCOMM Incorporated
InventorsGaurav Verma, Saksham Tandon
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Abstract
Aspects of the present disclosure provide a method generally including obtaining one or more built-in self-test (BIST) patterns, each pattern including a series of instructions, applying a compression scheme to generate one or more compressed BIST patterns, wherein the compression scheme encodes an operation and data field of instructions to generate encoded instructions, each encoded instruction having an identifier (ID) field and a variable number of data bytes, wherein the ID field identifies a type of the operation and indicates the variable number of data bytes, and storing the compressed BIST patterns.
Claims28
A method, comprising:
- obtaining one or more built-in self-test (BIST) patterns, each pattern including a series of instructions;
- applying a compression scheme to the one or more BIST patterns to generate one or more compressed BIST patterns, wherein the compression scheme encodes an operation and a data field of the series of instructions to generate encoded instructions, each encoded instruction having an identifier (ID) field and a variable number of data bytes, wherein the ID field identifies a type of the operation and indicates the variable number of data bytes;
- and
- storing the one or more compressed BIST patterns.
A method, comprising:
- obtaining an encoded instruction of a compressed built-in self-test (BIST) pattern, the compressed BIST pattern including a series of encoded instructions, the encoded instruction having an identifier (ID) field and a variable number of data bytes, wherein the ID field identifies a type of an operation and indicates the variable number of data bytes;
- applying a decompression scheme to the BIST pattern to generate a decoded instruction from the encoded instruction, wherein the decompression scheme decodes the ID field of the encoded instruction to reconstruct an operation and data field of the decoded instruction;
- and
- executing the decoded instruction.
An apparatus, comprising:
- memory comprising executable instructions;
- and
- one or more processors configured, individually or collectively, to execute the executable instructions and cause the apparatus to perform a method, the method comprising:
- obtaining one or more built-in self-test (BIST) patterns, each pattern including a series of instructions;
- applying a compression scheme to the one or more BIST patterns to generate one or more compressed BIST patterns, wherein the compression scheme encodes an operation and a data field of the series of instructions to generate encoded instructions, each encoded instruction having an identifier (ID) field and a variable number of data bytes, wherein the ID field identifies a type of the operation and indicates the variable number of data bytes;
- and
- storing the one or more compressed BIST patterns.
An apparatus, comprising:
- memory comprising executable instructions;
- and
- one or more processors configured, individually or collectively, to execute the executable instructions and cause the apparatus to perform a method, the method comprising:
- obtaining an encoded instruction of a compressed built-in self-test (BIST) pattern, the compressed BIST pattern including a series of encoded instructions, the encoded instruction having an identifier (ID) field and a variable number of data bytes, wherein the ID field identifies a type of an operation and indicates the variable number of data bytes;
- applying a decompression scheme to the BIST pattern to generate a decoded instruction from the encoded instruction, wherein the decompression scheme decodes the ID field of the encoded instruction to reconstruct an operation and data field of the decoded instruction;
- and
- executing the decoded instruction.
Dependencies are inferred from the claim text.