Clustering clock chain data for test-time reduction

A method for optimizing test circuitry in an integrated circuit, comprising:

• grouping tests to be performed by the test circuitry on the integrated circuit into a plurality of groups, the grouping being according to which clock pattern is to be applied as a test clock to scan chains in the integrated circuit for each test such that each test using a same clock pattern is in a same group;
• executing each group of tests by:
• loading a clock controller with a set of clock bits that configure the clock controller to generate the test clock as having the clock pattern utilized by that group of tests;
• and
• performing each test of that group of tests, using the test clock, without reconfiguring the clock controller with a different set of clock bits between different tests of that group of tests.

A test circuitry for an integrated circuit, comprising:

• an on-chip clock controller (OCC) configured to generate a test clock signal based on clock bits received from a clock chain, the test clock signal configured to operate the clock chain;
• wherein the clock chain is configured to receive m clock chain input bits from m of n input pins, where m is less than n, and to provide the clock bits to the OCC for generating the test clock signal;
• control circuitry configured to control the test circuitry to perform a plurality of tests on the integrated circuit, with each test being associated with the test clock signal having been generated by the OCC based on a given set of clock bits;
• and
• wherein ones of the plurality of tests associated with the test clock signal having been generated by the OCC based on the same given set of clock bits are performed after a single loading of that same given set of clock bits.