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US 2024/0369628 A1Published application
Embedded PHY (EPHY) IP Core for FPGA
AssigneeSanDisk Technologies LLC
InventorsDoron GANON, Eitan LERNER
Life of this patent
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Abstract
The present disclosure generally relates to an embedded physical layer (EPHY) for a field programmable gate array (FPGA). The EPHY for the FPGA is for a testing device that can receive and transmit in both the high speed PHYs, as well as low speed PHYs, such as MIPI PHYS (MPHYs), to meet universal flash storage (UFS) specifications. The testing device with the EPHY for the FPGA provides flexibility to support any specification updates without the need of application specific (ASIC) production cycles.
Claims20
A testing device, comprising:
- a field programmable gate array (FPGA);
- means to increase amplitude of a signal received from a device under testing (DUT) of a first speed to an amplitude of a signal of a second speed, wherein the means to increase is coupled to the FPGA;
- and
- means to decrease amplitude of a signal received from a DUT of the second speed to an amplitude of a signal of the first speed, wherein the means to decrease is coupled to the FPGA.
1 more element
A testing device, comprising:
- a field programmable gate array (FPGA);
- and
- an embedded physical layer (EPHY), the EPHY including:
- a logic portion comprising a low speed interface and a high speed interface, wherein the logic portion is disposed in the FPGA, and wherein the logic portion communicates with the FPGA through the low speed interface and the high speed interface;
- and
- a glue hardware portion, wherein the logic portion communicates with a device under test (DUT) through the glue hardware portion, the glue hardware portion including:
- a first differential amplifier configured to increase amplitude of a signal received from a device under testing (DUT) of a first speed to an amplitude of a signal of a second speed, wherein the first differential amplifier is coupled to the FPGA;
- and
- a second differential amplifier configured to decrease amplitude of a signal received from a DUT of the second speed to an amplitude of a signal of the first speed, wherein the second differential amplifier is coupled to the FPGA.
6 more elements
A testing device, comprising:
- a field programmable gate array (FPGA);
- and
- an embedded physical layer (EPHY), the EPHY including:
- a logic portion having a first logical phy and a second logical phy, wherein the logic portion is disposed in the FPGA, and wherein the logic portion communicates with the FPGA through the first and second logical phys;
- and
- a glue hardware portion, wherein the logic portion communicates with a device under test (DUT) through the glue hardware portion, the glue hardware portion including:
- a first differential amplifier configured to increase amplitude of a signal received from a device under testing (DUT) of a first speed to an amplitude of a signal of a second speed, wherein the first differential amplifier is coupled to the FPGA;
- a first multiplexer (MUX) coupled to the first differential amplifier;
- a second differential amplifier configured to decrease amplitude of a signal received from a DUT of the second speed to an amplitude of a signal of the first speed, wherein the second differential amplifier is coupled to the FPGA;
- and
- a second MUX coupled to the second differential amplifier.
8 more elements
Dependencies are inferred from the claim text.